1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013 George V. Neville-Neil
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#ifndef _NET_SFF8472_H_
30#define _NET_SFF8472_H_
31
32/*
33 * The following set of constants are from Document SFF-8472
34 * "Diagnostic Monitoring Interface for Optical Transceivers" revision
35 * 11.3 published by the SFF Committee on June 11, 2013
36 *
37 * The SFF standard defines two ranges of addresses, each 255 bytes
38 * long for the storage of data and diagnostics on cables, such as
39 * SFP+ optics and TwinAx cables. The ranges are defined in the
40 * following way:
41 *
42 * Base Address 0xa0 (Identification Data)
43 * 0-95 Serial ID Defined by SFP MSA
44 * 96-127 Vendor Specific Data
45 * 128-255 Reserved
46 *
47 * Base Address 0xa2 (Diagnostic Data)
48 * 0-55 Alarm and Warning Thresholds
49 * 56-95 Cal Constants
50 * 96-119 Real Time Diagnostic Interface
51 * 120-127 Vendor Specific
52 * 128-247 User Writable EEPROM
53 * 248-255 Vendor Specific
54 *
55 * Note that not all addresses are supported. Where support is
56 * optional this is noted and instructions for checking for the
57 * support are supplied.
58 *
59 * All these values are read across an I2C (i squared C) bus. Any
60 * device wishing to read these addresses must first have support for
61 * i2c calls. The Chelsio T4/T5 driver (dev/cxgbe) is one such
62 * driver.
63 */
64
65/* Table 3.1 Two-wire interface ID: Data Fields */
66
67enum {
68 SFF_8472_BASE = 0xa0, /* Base address for all our queries. */
69 SFF_8472_ID = 0, /* Transceiver Type (Table 3.2) */
70 SFF_8472_EXT_ID = 1, /* Extended transceiver type (Table 3.3) */
71 SFF_8472_CONNECTOR = 2, /* Connector type (Table 3.4) */
72 SFF_8472_TRANS_START = 3, /* Elec or Optical Compatibility
73 * (Table 3.5) */
74 SFF_8472_TRANS_END = 10,
75 SFF_8472_ENCODING = 11, /* Encoding Code for high speed
76 * serial encoding algorithm (see
77 * Table 3.6) */
78 SFF_8472_BITRATE = 12, /* Nominal signaling rate, units
79 * of 100MBd. (see details for
80 * rates > 25.0Gb/s) */
81 SFF_8472_RATEID = 13, /* Type of rate select
82 * functionality (see Table
83 * 3.6a) */
84 SFF_8472_LEN_SMF_KM = 14, /* Link length supported for single
85 * mode fiber, units of km */
86 SFF_8472_LEN_SMF = 15, /* Link length supported for single
87 * mode fiber, units of 100 m */
88 SFF_8472_LEN_50UM = 16, /* Link length supported for 50 um
89 * OM2 fiber, units of 10 m */
90 SFF_8472_LEN_625UM = 17, /* Link length supported for 62.5
91 * um OM1 fiber, units of 10 m */
92 SFF_8472_LEN_OM4 = 18, /* Link length supported for 50um
93 * OM4 fiber, units of 10m.
94 * Alternatively copper or direct
95 * attach cable, units of m */
96 SFF_8472_LEN_OM3 = 19, /* Link length supported for 50 um OM3 fiber, units of 10 m */
97 SFF_8472_VENDOR_START = 20, /* Vendor name [Address A0h, Bytes
98 * 20-35] */
99 SFF_8472_VENDOR_END = 35,
100 SFF_8472_TRANS = 36, /* Transceiver Code for electronic
101 * or optical compatibility (see
102 * Table 3.5) */
103 SFF_8472_VENDOR_OUI_START = 37, /* Vendor OUI SFP vendor IEEE
104 * company ID */
105 SFF_8472_VENDOR_OUI_END = 39,
106 SFF_8472_PN_START = 40, /* Vendor PN */
107 SFF_8472_PN_END = 55,
108 SFF_8472_REV_START = 56, /* Vendor Revision */
109 SFF_8472_REV_END = 59,
110 SFF_8472_WAVELEN_START = 60, /* Wavelength Laser wavelength
111 * (Passive/Active Cable
112 * Specification Compliance) */
113 SFF_8472_WAVELEN_END = 61,
114 SFF_8472_CC_BASE = 63, /* CC_BASE Check code for Base ID
115 * Fields (addresses 0 to 62) */
116
117/*
118 * Extension Fields (optional) check the options before reading other
119 * addresses.
120 */
121 SFF_8472_OPTIONS_MSB = 64, /* Options Indicates which optional
122 * transceiver signals are
123 * implemented */
124 SFF_8472_OPTIONS_LSB = 65, /* (see Table 3.7) */
125 SFF_8472_BR_MAX = 66, /* BR max Upper bit rate margin,
126 * units of % (see details for
127 * rates > 25.0Gb/s) */
128 SFF_8472_BR_MIN = 67, /* Lower bit rate margin, units of
129 * % (see details for rates >
130 * 25.0Gb/s) */
131 SFF_8472_SN_START = 68, /* Vendor SN [Address A0h, Bytes 68-83] */
132 SFF_8472_SN_END = 83,
133 SFF_8472_DATE_START = 84, /* Date code Vendor’s manufacturing
134 * date code (see Table 3.8) */
135 SFF_8472_DATE_END = 91,
136 SFF_8472_DIAG_TYPE = 92, /* Diagnostic Monitoring Type
137 * Indicates which type of
138 * diagnostic monitoring is
139 * implemented (if any) in the
140 * transceiver (see Table 3.9)
141 */
142
143 SFF_8472_ENHANCED = 93, /* Enhanced Options Indicates which
144 * optional enhanced features are
145 * implemented (if any) in the
146 * transceiver (see Table 3.10) */
147 SFF_8472_COMPLIANCE = 94, /* SFF-8472 Compliance Indicates
148 * which revision of SFF-8472 the
149 * transceiver complies with. (see
150 * Table 3.12)*/
151 SFF_8472_CC_EXT = 95, /* Check code for the Extended ID
152 * Fields (addresses 64 to 94)
153 */
154
155 SFF_8472_VENDOR_RSRVD_START = 96,
156 SFF_8472_VENDOR_RSRVD_END = 127,
157
158 SFF_8472_RESERVED_START = 128,
159 SFF_8472_RESERVED_END = 255
160};
161
162#define SFF_8472_DIAG_IMPL (1 << 6) /* Required to be 1 */
163#define SFF_8472_DIAG_INTERNAL (1 << 5) /* Internal measurements. */
164#define SFF_8472_DIAG_EXTERNAL (1 << 4) /* External measurements. */
165#define SFF_8472_DIAG_POWER (1 << 3) /* Power measurement type */
166#define SFF_8472_DIAG_ADDR_CHG (1 << 2) /* Address change required.
167 * See SFF-8472 doc. */
168
169 /*
170 * Diagnostics are available at the two wire address 0xa2. All
171 * diagnostics are OPTIONAL so you should check 0xa0 registers 92 to
172 * see which, if any are supported.
173 */
174
175enum {SFF_8472_DIAG = 0xa2}; /* Base address for diagnostics. */
176
177 /*
178 * Table 3.15 Alarm and Warning Thresholds All values are 2 bytes
179 * and MUST be read in a single read operation starting at the MSB
180 */
181
182enum {
183 SFF_8472_TEMP_HIGH_ALM = 0, /* Temp High Alarm */
184 SFF_8472_TEMP_LOW_ALM = 2, /* Temp Low Alarm */
185 SFF_8472_TEMP_HIGH_WARN = 4, /* Temp High Warning */
186 SFF_8472_TEMP_LOW_WARN = 6, /* Temp Low Warning */
187 SFF_8472_VOLTAGE_HIGH_ALM = 8, /* Voltage High Alarm */
188 SFF_8472_VOLTAGE_LOW_ALM = 10, /* Voltage Low Alarm */
189 SFF_8472_VOLTAGE_HIGH_WARN = 12, /* Voltage High Warning */
190 SFF_8472_VOLTAGE_LOW_WARN = 14, /* Voltage Low Warning */
191 SFF_8472_BIAS_HIGH_ALM = 16, /* Bias High Alarm */
192 SFF_8472_BIAS_LOW_ALM = 18, /* Bias Low Alarm */
193 SFF_8472_BIAS_HIGH_WARN = 20, /* Bias High Warning */
194 SFF_8472_BIAS_LOW_WARN = 22, /* Bias Low Warning */
195 SFF_8472_TX_POWER_HIGH_ALM = 24, /* TX Power High Alarm */
196 SFF_8472_TX_POWER_LOW_ALM = 26, /* TX Power Low Alarm */
197 SFF_8472_TX_POWER_HIGH_WARN = 28, /* TX Power High Warning */
198 SFF_8472_TX_POWER_LOW_WARN = 30, /* TX Power Low Warning */
199 SFF_8472_RX_POWER_HIGH_ALM = 32, /* RX Power High Alarm */
200 SFF_8472_RX_POWER_LOW_ALM = 34, /* RX Power Low Alarm */
201 SFF_8472_RX_POWER_HIGH_WARN = 36, /* RX Power High Warning */
202 SFF_8472_RX_POWER_LOW_WARN = 38, /* RX Power Low Warning */
203
204 SFF_8472_RX_POWER4 = 56, /* Rx_PWR(4) Single precision
205 * floating point calibration data
206 * - Rx optical power. Bit 7 of
207 * byte 56 is MSB. Bit 0 of byte
208 * 59 is LSB. Rx_PWR(4) should be
209 * set to zero for “internally
210 * calibrated” devices. */
211 SFF_8472_RX_POWER3 = 60, /* Rx_PWR(3) Single precision
212 * floating point calibration data
213 * - Rx optical power. Bit 7 of
214 * byte 60 is MSB. Bit 0 of byte 63
215 * is LSB. Rx_PWR(3) should be set
216 * to zero for “internally
217 * calibrated” devices.*/
218 SFF_8472_RX_POWER2 = 64, /* Rx_PWR(2) Single precision
219 * floating point calibration data,
220 * Rx optical power. Bit 7 of byte
221 * 64 is MSB, bit 0 of byte 67 is
222 * LSB. Rx_PWR(2) should be set to
223 * zero for “internally calibrated”
224 * devices. */
225 SFF_8472_RX_POWER1 = 68, /* Rx_PWR(1) Single precision
226 * floating point calibration data,
227 * Rx optical power. Bit 7 of byte
228 * 68 is MSB, bit 0 of byte 71 is
229 * LSB. Rx_PWR(1) should be set to
230 * 1 for “internally calibrated”
231 * devices. */
232 SFF_8472_RX_POWER0 = 72, /* Rx_PWR(0) Single precision
233 * floating point calibration data,
234 * Rx optical power. Bit 7 of byte
235 * 72 is MSB, bit 0 of byte 75 is
236 * LSB. Rx_PWR(0) should be set to
237 * zero for “internally calibrated”
238 * devices. */
239 SFF_8472_TX_I_SLOPE = 76, /* Tx_I(Slope) Fixed decimal
240 * (unsigned) calibration data,
241 * laser bias current. Bit 7 of
242 * byte 76 is MSB, bit 0 of byte 77
243 * is LSB. Tx_I(Slope) should be
244 * set to 1 for “internally
245 * calibrated” devices. */
246 SFF_8472_TX_I_OFFSET = 78, /* Tx_I(Offset) Fixed decimal
247 * (signed two’s complement)
248 * calibration data, laser bias
249 * current. Bit 7 of byte 78 is
250 * MSB, bit 0 of byte 79 is
251 * LSB. Tx_I(Offset) should be set
252 * to zero for “internally
253 * calibrated” devices. */
254 SFF_8472_TX_POWER_SLOPE = 80, /* Tx_PWR(Slope) Fixed decimal
255 * (unsigned) calibration data,
256 * transmitter coupled output
257 * power. Bit 7 of byte 80 is MSB,
258 * bit 0 of byte 81 is LSB.
259 * Tx_PWR(Slope) should be set to 1
260 * for “internally calibrated”
261 * devices. */
262 SFF_8472_TX_POWER_OFFSET = 82, /* Tx_PWR(Offset) Fixed decimal
263 * (signed two’s complement)
264 * calibration data, transmitter
265 * coupled output power. Bit 7 of
266 * byte 82 is MSB, bit 0 of byte 83
267 * is LSB. Tx_PWR(Offset) should be
268 * set to zero for “internally
269 * calibrated” devices. */
270 SFF_8472_T_SLOPE = 84, /* T (Slope) Fixed decimal
271 * (unsigned) calibration data,
272 * internal module temperature. Bit
273 * 7 of byte 84 is MSB, bit 0 of
274 * byte 85 is LSB. T(Slope) should
275 * be set to 1 for “internally
276 * calibrated” devices. */
277 SFF_8472_T_OFFSET = 86, /* T (Offset) Fixed decimal (signed
278 * two’s complement) calibration
279 * data, internal module
280 * temperature. Bit 7 of byte 86 is
281 * MSB, bit 0 of byte 87 is LSB.
282 * T(Offset) should be set to zero
283 * for “internally calibrated”
284 * devices. */
285 SFF_8472_V_SLOPE = 88, /* V (Slope) Fixed decimal
286 * (unsigned) calibration data,
287 * internal module supply
288 * voltage. Bit 7 of byte 88 is
289 * MSB, bit 0 of byte 89 is
290 * LSB. V(Slope) should be set to 1
291 * for “internally calibrated”
292 * devices. */
293 SFF_8472_V_OFFSET = 90, /* V (Offset) Fixed decimal (signed
294 * two’s complement) calibration
295 * data, internal module supply
296 * voltage. Bit 7 of byte 90 is
297 * MSB. Bit 0 of byte 91 is
298 * LSB. V(Offset) should be set to
299 * zero for “internally calibrated”
300 * devices. */
301 SFF_8472_CHECKSUM = 95, /* Checksum Byte 95 contains the
302 * low order 8 bits of the sum of
303 * bytes 0 – 94. */
304 /* Internal measurements. */
305
306 SFF_8472_TEMP = 96, /* Internally measured module temperature. */
307 SFF_8472_VCC = 98, /* Internally measured supply
308 * voltage in transceiver.
309 */
310 SFF_8472_TX_BIAS = 100, /* Internally measured TX Bias Current. */
311 SFF_8472_TX_POWER = 102, /* Measured TX output power. */
312 SFF_8472_RX_POWER = 104, /* Measured RX input power. */
313
314 SFF_8472_STATUS = 110 /* See below */
315};
316 /* Status Bits Described */
317
318/*
319 * TX Disable State Digital state of the TX Disable Input Pin. Updated
320 * within 100ms of change on pin.
321 */
322#define SFF_8472_STATUS_TX_DISABLE (1 << 7)
323
324/*
325 * Select Read/write bit that allows software disable of
326 * laser. Writing ‘1’ disables laser. See Table 3.11 for
327 * enable/disable timing requirements. This bit is “OR”d with the hard
328 * TX_DISABLE pin value. Note, per SFP MSA TX_DISABLE pin is default
329 * enabled unless pulled low by hardware. If Soft TX Disable is not
330 * implemented, the transceiver ignores the value of this bit. Default
331 * power up value is zero/low.
332 */
333#define SFF_8472_STATUS_SOFT_TX_DISABLE (1 << 6)
334
335/*
336 * RS(1) State Digital state of SFP input pin AS(1) per SFF-8079 or
337 * RS(1) per SFF-8431. Updated within 100ms of change on pin. See A2h
338 * Byte 118, Bit 3 for Soft RS(1) Select control information.
339 */
340#define SFF_8472_RS_STATE (1 << 5)
341
342/*
343 * Rate_Select State [aka. “RS(0)”] Digital state of the SFP
344 * Rate_Select Input Pin. Updated within 100ms of change on pin. Note:
345 * This pin is also known as AS(0) in SFF-8079 and RS(0) in SFF-8431.
346 */
347#define SFF_8472_STATUS_SELECT_STATE (1 << 4)
348
349/*
350 * Read/write bit that allows software rate select control. Writing
351 * ‘1’ selects full bandwidth operation. This bit is “OR’d with the
352 * hard Rate_Select, AS(0) or RS(0) pin value. See Table 3.11 for
353 * timing requirements. Default at power up is logic zero/low. If Soft
354 * Rate Select is not implemented, the transceiver ignores the value
355 * of this bit. Note: Specific transceiver behaviors of this bit are
356 * identified in Table 3.6a and referenced documents. See Table 3.18a,
357 * byte 118, bit 3 for Soft RS(1) Select.
358 */
359#define SFF_8472_STATUS_SOFT_RATE_SELECT (1 << 3)
360
361/*
362 * TX Fault State Digital state of the TX Fault Output Pin. Updated
363 * within 100ms of change on pin.
364 */
365#define SFF_8472_STATUS_TX_FAULT_STATE (1 << 2)
366
367/*
368 * Digital state of the RX_LOS Output Pin. Updated within 100ms of
369 * change on pin.
370 */
371#define SFF_8472_STATUS_RX_LOS (1 << 1)
372
373/*
374 * Indicates transceiver has achieved power up and data is ready. Bit
375 * remains high until data is ready to be read at which time the
376 * device sets the bit low.
377 */
378#define SFF_8472_STATUS_DATA_READY (1 << 0)
379
380/*
381 * Table 3.2 Identifier values.
382 * Identifier constants has taken from SFF-8024 rev 4.6 table 4.1
383 * (as referenced by table 3.2 footer)
384 * */
385enum {
386 SFF_8024_ID_UNKNOWN = 0x0, /* Unknown or unspecified */
387 SFF_8024_ID_GBIC = 0x1, /* GBIC */
388 SFF_8024_ID_SFF = 0x2, /* Module soldered to motherboard (ex: SFF)*/
389 SFF_8024_ID_SFP = 0x3, /* SFP or SFP “Plus” */
390 SFF_8024_ID_XBI = 0x4, /* 300 pin XBI */
391 SFF_8024_ID_XENPAK = 0x5, /* Xenpak */
392 SFF_8024_ID_XFP = 0x6, /* XFP */
393 SFF_8024_ID_XFF = 0x7, /* XFF */
394 SFF_8024_ID_XFPE = 0x8, /* XFP-E */
395 SFF_8024_ID_XPAK = 0x9, /* XPAk */
396 SFF_8024_ID_X2 = 0xA, /* X2 */
397 SFF_8024_ID_DWDM_SFP = 0xB, /* DWDM-SFP */
398 SFF_8024_ID_QSFP = 0xC, /* QSFP */
399 SFF_8024_ID_QSFPPLUS = 0xD, /* QSFP+ or later */
400 SFF_8024_ID_CXP = 0xE, /* CXP */
401 SFF_8024_ID_HD4X = 0xF, /* Shielded Mini Multilane HD 4X */
402 SFF_8024_ID_HD8X = 0x10, /* Shielded Mini Multilane HD 8X */
403 SFF_8024_ID_QSFP28 = 0x11, /* QSFP28 or later */
404 SFF_8024_ID_CXP2 = 0x12, /* CXP2 (aka CXP28) */
405 SFF_8024_ID_CDFP = 0x13, /* CDFP (Style 1/Style 2) */
406 SFF_8024_ID_SMM4 = 0x14, /* Shielded Mini Multilate HD 4X Fanout */
407 SFF_8024_ID_SMM8 = 0x15, /* Shielded Mini Multilate HD 8X Fanout */
408 SFF_8024_ID_CDFP3 = 0x16, /* CDFP (Style3) */
409 SFF_8024_ID_MICROQSFP = 0x17, /* microQSFP */
410 SFF_8024_ID_QSFP_DD = 0x18, /* QSFP-DD 8X Pluggable Transceiver */
411 SFF_8024_ID_OSFP8X = 0x19, /* OSFP 8X Pluggable Transceiver */
412 SFF_8024_ID_SFP_DD = 0x1A, /* SFP-DD 2X Pluggable Transceiver */
413 SFF_8024_ID_DSFP = 0x1B, /* DSFP Dual SFF Pluggable Transceiver */
414 SFF_8024_ID_X4ML = 0x1C, /* x4 MiniLink/OcuLink */
415 SFF_8024_ID_X8ML = 0x1D, /* x8 MiniLink */
416 SFF_8024_ID_QSFP_CMIS = 0x1E, /* QSFP+ or later w/ Common Management
417 Interface Specification */
418 SFF_8024_ID_LAST = SFF_8024_ID_QSFP_CMIS
419};
420
421#if defined(_WANT_SFF_8024_ID) || defined(_WANT_SFF_8472_ID)
422static const char *sff_8024_id[SFF_8024_ID_LAST + 1] = {
423 "Unknown",
424 "GBIC",
425 "SFF",
426 "SFP/SFP+/SFP28",
427 "XBI",
428 "Xenpak",
429 "XFP",
430 "XFF",
431 "XFP-E",
432 "XPAK",
433 "X2",
434 "DWDM-SFP/SFP+",
435 "QSFP",
436 "QSFP+",
437 "CXP",
438 "HD4X",
439 "HD8X",
440 "QSFP28",
441 "CXP2",
442 "CDFP",
443 "SMM4",
444 "SMM8",
445 "CDFP3",
446 "microQSFP",
447 "QSFP-DD",
448 "QSFP8X",
449 "SFP-DD",
450 "DSFP",
451 "x4MiniLink/OcuLink",
452 "x8MiniLink",
453 "QSFP+(CIMS)"
454};
455#endif
456
457/* Keep compatibility with old definitions */
458#define SFF_8472_ID_UNKNOWN SFF_8024_ID_UNKNOWN
459#define SFF_8472_ID_GBIC SFF_8024_ID_GBIC
460#define SFF_8472_ID_SFF SFF_8024_ID_SFF
461#define SFF_8472_ID_SFP SFF_8024_ID_SFP
462#define SFF_8472_ID_XBI SFF_8024_ID_XBI
463#define SFF_8472_ID_XENPAK SFF_8024_ID_XENPAK
464#define SFF_8472_ID_XFP SFF_8024_ID_XFP
465#define SFF_8472_ID_XFF SFF_8024_ID_XFF
466#define SFF_8472_ID_XFPE SFF_8024_ID_XFPE
467#define SFF_8472_ID_XPAK SFF_8024_ID_XPAK
468#define SFF_8472_ID_X2 SFF_8024_ID_X2
469#define SFF_8472_ID_DWDM_SFP SFF_8024_ID_DWDM_SFP
470#define SFF_8472_ID_QSFP SFF_8024_ID_QSFP
471#define SFF_8472_ID_LAST SFF_8024_ID_LAST
472
473#define sff_8472_id sff_8024_id
474
475/*
476 * Table 3.9 Diagnostic Monitoring Type (byte 92)
477 * bits described.
478 */
479
480/*
481 * Digital diagnostic monitoring implemented.
482 * Set to 1 for transceivers implementing DDM.
483 */
484#define SFF_8472_DDM_DONE (1 << 6)
485
486/*
487 * Measurements are internally calibrated.
488 */
489#define SFF_8472_DDM_INTERNAL (1 << 5)
490
491/*
492 * Measurements are externally calibrated.
493 */
494#define SFF_8472_DDM_EXTERNAL (1 << 4)
495
496/*
497 * Received power measurement type
498 * 0 = OMA, 1 = average power
499 */
500#define SFF_8472_DDM_PMTYPE (1 << 3)
501
502/* Table 3.13 and 3.14 Temperature Conversion Values */
503#define SFF_8472_TEMP_SIGN (1 << 15)
504#define SFF_8472_TEMP_SHIFT 8
505#define SFF_8472_TEMP_MSK 0xEF00
506#define SFF_8472_TEMP_FRAC 0x00FF
507
508/* Internal Callibration Conversion factors */
509
510/*
511 * Represented as a 16 bit unsigned integer with the voltage defined
512 * as the full 16 bit value (0 – 65535) with LSB equal to 100 uVolt,
513 * yielding a total range of 0 to +6.55 Volts.
514 */
515#define SFF_8472_VCC_FACTOR 10000.0
516
517/*
518 * Represented as a 16 bit unsigned integer with the current defined
519 * as the full 16 bit value (0 – 65535) with LSB equal to 2 uA,
520 * yielding a total range of 0 to 131 mA.
521 */
522
523#define SFF_8472_BIAS_FACTOR 2000.0
524
525/*
526 * Represented as a 16 bit unsigned integer with the power defined as
527 * the full 16 bit value (0 – 65535) with LSB equal to 0.1 uW,
528 * yielding a total range of 0 to 6.5535 mW (~ -40 to +8.2 dBm).
529 */
530
531#define SFF_8472_POWER_FACTOR 10000.0
532
533#endif