1/* $NetBSD: cpuregs.h,v 1.116 2021/11/16 06:11:52 simonb Exp $ */
2
3/*
4 * Copyright (c) 2009 Miodrag Vallat.
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19/*
20 * Copyright (c) 1992, 1993
21 * The Regents of the University of California. All rights reserved.
22 *
23 * This code is derived from software contributed to Berkeley by
24 * Ralph Campbell and Rick Macklem.
25 *
26 * Redistribution and use in source and binary forms, with or without
27 * modification, are permitted provided that the following conditions
28 * are met:
29 * 1. Redistributions of source code must retain the above copyright
30 * notice, this list of conditions and the following disclaimer.
31 * 2. Redistributions in binary form must reproduce the above copyright
32 * notice, this list of conditions and the following disclaimer in the
33 * documentation and/or other materials provided with the distribution.
34 * 3. Neither the name of the University nor the names of its contributors
35 * may be used to endorse or promote products derived from this software
36 * without specific prior written permission.
37 *
38 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
39 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
40 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
41 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
42 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
43 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
44 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
45 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
46 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
47 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
48 * SUCH DAMAGE.
49 *
50 * @(#)machConst.h 8.1 (Berkeley) 6/10/93
51 *
52 * machConst.h --
53 *
54 * Machine dependent constants.
55 *
56 * Copyright (C) 1989 Digital Equipment Corporation.
57 * Permission to use, copy, modify, and distribute this software and
58 * its documentation for any purpose and without fee is hereby granted,
59 * provided that the above copyright notice appears in all copies.
60 * Digital Equipment Corporation makes no representations about the
61 * suitability of this software for any purpose. It is provided "as is"
62 * without express or implied warranty.
63 *
64 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machConst.h,
65 * v 9.2 89/10/21 15:55:22 jhh Exp SPRITE (DECWRL)
66 * from: Header: /sprite/src/kernel/mach/ds3100.md/RCS/machAddrs.h,
67 * v 1.2 89/08/15 18:28:21 rab Exp SPRITE (DECWRL)
68 * from: Header: /sprite/src/kernel/vm/ds3100.md/RCS/vmPmaxConst.h,
69 * v 9.1 89/09/18 17:33:00 shirriff Exp SPRITE (DECWRL)
70 */
71
72#ifndef _MIPS_CPUREGS_H_
73#define _MIPS_CPUREGS_H_
74
75#include <sys/cdefs.h> /* For __CONCAT() */
76
77#if defined(_KERNEL_OPT)
78#include "opt_cputype.h"
79#endif
80
81/*
82 * Address space.
83 * 32-bit mips CPUS partition their 32-bit address space into four segments:
84 *
85 * kuseg 0x00000000 - 0x7fffffff User virtual mem, mapped
86 * kseg0 0x80000000 - 0x9fffffff Physical memory, cached, unmapped
87 * kseg1 0xa0000000 - 0xbfffffff Physical memory, uncached, unmapped
88 * kseg2 0xc0000000 - 0xffffffff kernel-virtual, mapped
89 *
90 * mips1 physical memory is limited to 512Mbytes, which is
91 * doubly mapped in kseg0 (cached) and kseg1 (uncached.)
92 * Caching of mapped addresses is controlled by bits in the TLB entry.
93 */
94
95#ifdef _LP64
96#define MIPS_XUSEG_START (0L << 62)
97#define MIPS_XUSEG_P(x) (((uint64_t)(x) >> 62) == 0)
98#define MIPS_USEG_P(x) ((uintptr_t)(x) < 0x80000000L)
99#define MIPS_XSSEG_START (1L << 62)
100#define MIPS_XSSEG_P(x) (((uint64_t)(x) >> 62) == 1)
101#endif
102
103/*
104 * MIPS addresses are signed and we defining as negative so that
105 * in LP64 kern they get sign-extended correctly.
106 */
107#ifndef _LOCORE
108#define MIPS_KSEG0_START (-0x7fffffffL-1) /* 0x80000000 */
109#define MIPS_KSEG1_START -0x60000000L /* 0xa0000000 */
110#define MIPS_KSEG2_START -0x40000000L /* 0xc0000000 */
111#define MIPS_MAX_MEM_ADDR -0x42000000L /* 0xbe000000 */
112#define MIPS_RESERVED_ADDR -0x40380000L /* 0xbfc80000 */
113#endif
114
115#define MIPS_PHYS_MASK 0x1fffffff
116
117#define MIPS_KSEG0_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK)
118#define MIPS_PHYS_TO_KSEG0(x) ((intptr_t)((x) + MIPS_KSEG0_START))
119#define MIPS_KSEG1_TO_PHYS(x) ((uintptr_t)(x) & MIPS_PHYS_MASK)
120#define MIPS_PHYS_TO_KSEG1(x) ((intptr_t)(x) | (intptr_t)MIPS_KSEG1_START)
121
122#define MIPS_KSEG0_P(x) (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG0_START)
123#define MIPS_KSEG1_P(x) (((intptr_t)(x) & ~MIPS_PHYS_MASK) == MIPS_KSEG1_START)
124#define MIPS_KSEG2_P(x) ((uintptr_t)MIPS_KSEG2_START <= (uintptr_t)(x))
125
126/* Map virtual address to index in mips3 r4k virtually-indexed cache */
127#define MIPS3_VA_TO_CINDEX(x) \
128 (((intptr_t)(x) & 0xffffff) | MIPS_KSEG0_START)
129
130#ifndef _LOCORE
131#define MIPS_XSEG_MASK (0x3fffffffffffffffLL)
132#define MIPS_XKSEG_START (0x3ULL << 62)
133#define MIPS_XKSEG_P(x) (((uint64_t)(x) >> 62) == 3)
134
135#define MIPS_XKPHYS_START (0x2ULL << 62)
136#define MIPS_PHYS_TO_XKPHYS_UNCACHED(x) \
137 (MIPS_XKPHYS_START | ((uint64_t)(CCA_UNCACHED) << 59) | (x))
138#define MIPS_PHYS_TO_XKPHYS_ACC(x) \
139 (MIPS_XKPHYS_START | ((uint64_t)(mips_options.mips3_cca_devmem) << 59) | (x))
140#define MIPS_PHYS_TO_XKPHYS_CACHED(x) \
141 (mips_options.mips3_xkphys_cached | (x))
142#define MIPS_PHYS_TO_XKPHYS(cca,x) \
143 (MIPS_XKPHYS_START | ((uint64_t)(cca) << 59) | (x))
144#define MIPS_XKPHYS_TO_PHYS(x) ((uint64_t)(x) & 0x07ffffffffffffffLL)
145#define MIPS_XKPHYS_TO_CCA(x) (((uint64_t)(x) >> 59) & 7)
146#define MIPS_XKPHYS_P(x) (((uint64_t)(x) >> 62) == 2)
147#endif /* _LOCORE */
148
149#define CCA_UNCACHED 2
150#define CCA_CACHEABLE 3 /* cacheable non-coherent */
151#define CCA_SB_CACHEABLE_COHERENT 5 /* cacheable coherent (SiByte ext) */
152#define CCA_ACCEL 7 /* non-cached, write combining */
153
154/* CPU dependent mtc0 hazard hook */
155#if (MIPS32R2 + MIPS64R2) > 0
156# if (MIPS1 + MIPS3 + MIPS32 + MIPS64) == 0
157# define COP0_SYNC sll $0,$0,3 /* EHB */
158# define JR_HB_RA .set push; .set mips32r2; jr.hb ra; nop; .set pop
159# else
160# define COP0_SYNC sll $0,$0,1; sll $0,$0,1; sll $0,$0,3
161# define JR_HB_RA sll $0,$0,1; sll $0,$0,1; jr ra; sll $0,$0,3
162# endif
163#elif (MIPS32 + MIPS64) > 0
164# define COP0_SYNC sll $0,$0,1; sll $0,$0,1; sll $0,$0,1
165# define JR_HB_RA sll $0,$0,1; sll $0,$0,1; jr ra; sll $0,$0,1
166#elif MIPS3 > 0
167# define COP0_SYNC nop; nop; nop
168# define JR_HB_RA nop; nop; jr ra; nop
169#else
170# define COP0_SYNC nop
171# define JR_HB_RA jr ra; nop
172#endif
173#define COP0_HAZARD_FPUENABLE nop; nop; nop; nop;
174
175/*
176 * The bits in the cause register.
177 *
178 * Bits common to r3000 and r4000:
179 *
180 * MIPS_CR_BR_DELAY Exception happened in branch delay slot.
181 * MIPS_CR_COP_ERR Coprocessor error.
182 * MIPS_CR_IP Interrupt pending bits defined below.
183 * (same meaning as in CAUSE register).
184 * MIPS_CR_EXC_CODE The exception type (see exception codes below).
185 *
186 * Differences:
187 * r3k has 4 bits of exception type, r4k has 5 bits.
188 */
189#define MIPS_CR_BR_DELAY 0x80000000
190#define MIPS_CR_COP_ERR 0x30000000
191#define MIPS_CR_COP_ERR_CU1 1
192#define MIPS_CR_COP_ERR_CU2 2
193#define MIPS_CR_COP_ERR_CU3 3
194#define MIPS1_CR_EXC_CODE 0x0000003C /* four bits */
195#define MIPS3_CR_EXC_CODE 0x0000007C /* five bits */
196#define MIPS_CR_IP 0x0000FF00
197#define MIPS_CR_EXC_CODE_SHIFT 2
198
199/*
200 * The bits in the status register. All bits are active when set to 1.
201 *
202 * R3000 status register fields:
203 * MIPS_SR_COP_USABILITY Control the usability of the four coprocessors.
204 * MIPS_SR_TS TLB shutdown.
205 *
206 * MIPS_SR_INT_IE Master (current) interrupt enable bit.
207 *
208 * Differences:
209 * r3k has cache control is via frobbing SR register bits, whereas the
210 * r4k cache control is via explicit instructions.
211 * r3k has a 3-entry stack of kernel/user bits, whereas the
212 * r4k has kernel/supervisor/user.
213 */
214#define MIPS_SR_COP_USABILITY 0xf0000000
215#define MIPS_SR_COP_0_BIT 0x10000000
216#define MIPS_SR_COP_1_BIT 0x20000000
217#define MIPS_SR_COP_2_BIT 0x40000000
218
219 /* r4k and r3k differences, see below */
220
221#define MIPS_SR_MX 0x01000000 /* MIPS64 */
222#define MIPS_SR_PX 0x00800000 /* MIPS64 */
223#define MIPS_SR_BEV 0x00400000 /* Use boot exception vector */
224#define MIPS_SR_TS 0x00200000
225
226 /* r4k and r3k differences, see below */
227
228#define MIPS_SR_INT_IE 0x00000001
229/*#define MIPS_SR_MBZ 0x0f8000c0*/ /* Never used, true for r3k */
230/*#define MIPS_SR_INT_MASK 0x0000ff00*/
231
232
233/*
234 * The R2000/R3000-specific status register bit definitions.
235 * all bits are active when set to 1.
236 *
237 * MIPS_SR_PARITY_ERR Parity error.
238 * MIPS_SR_CACHE_MISS Most recent D-cache load resulted in a miss.
239 * MIPS_SR_PARITY_ZERO Zero replaces outgoing parity bits.
240 * MIPS_SR_SWAP_CACHES Swap I-cache and D-cache.
241 * MIPS_SR_ISOL_CACHES Isolate D-cache from main memory.
242 * Interrupt enable bits defined below.
243 * MIPS_SR_KU_OLD Old kernel/user mode bit. 1 => user mode.
244 * MIPS_SR_INT_ENA_OLD Old interrupt enable bit.
245 * MIPS_SR_KU_PREV Previous kernel/user mode bit. 1 => user mode.
246 * MIPS_SR_INT_ENA_PREV Previous interrupt enable bit.
247 * MIPS_SR_KU_CUR Current kernel/user mode bit. 1 => user mode.
248 */
249
250#define MIPS1_PARITY_ERR 0x00100000
251#define MIPS1_CACHE_MISS 0x00080000
252#define MIPS1_PARITY_ZERO 0x00040000
253#define MIPS1_SWAP_CACHES 0x00020000
254#define MIPS1_ISOL_CACHES 0x00010000
255
256#define MIPS1_SR_KU_OLD 0x00000020 /* 2nd stacked KU/IE*/
257#define MIPS1_SR_INT_ENA_OLD 0x00000010 /* 2nd stacked KU/IE*/
258#define MIPS1_SR_KU_PREV 0x00000008 /* 1st stacked KU/IE*/
259#define MIPS1_SR_INT_ENA_PREV 0x00000004 /* 1st stacked KU/IE*/
260#define MIPS1_SR_KU_CUR 0x00000002 /* current KU */
261
262/* backwards compatibility */
263#define MIPS_SR_PARITY_ERR MIPS1_PARITY_ERR
264#define MIPS_SR_CACHE_MISS MIPS1_CACHE_MISS
265#define MIPS_SR_PARITY_ZERO MIPS1_PARITY_ZERO
266#define MIPS_SR_SWAP_CACHES MIPS1_SWAP_CACHES
267#define MIPS_SR_ISOL_CACHES MIPS1_ISOL_CACHES
268
269#define MIPS_SR_KU_OLD MIPS1_SR_KU_OLD
270#define MIPS_SR_INT_ENA_OLD MIPS1_SR_INT_ENA_OLD
271#define MIPS_SR_KU_PREV MIPS1_SR_KU_PREV
272#define MIPS_SR_KU_CUR MIPS1_SR_KU_CUR
273#define MIPS_SR_INT_ENA_PREV MIPS1_SR_INT_ENA_PREV
274
275/*
276 * R4000 status register bit definitions,
277 * where different from r2000/r3000.
278 */
279#define MIPS3_SR_XX 0x80000000
280#define MIPS3_SR_RP 0x08000000
281#define MIPS3_SR_FR 0x04000000
282#define MIPS3_SR_RE 0x02000000
283
284#define MIPS3_SR_DIAG_DL 0x01000000 /* QED 52xx */
285#define MIPS3_SR_DIAG_IL 0x00800000 /* QED 52xx */
286#define MIPS3_SR_PX 0x00800000 /* MIPS64 */
287#define MIPS3_SR_SR 0x00100000
288#define MIPS3_SR_NMI 0x00080000 /* MIPS32/64 */
289#define MIPS3_SR_DIAG_CH 0x00040000
290#define MIPS3_SR_DIAG_CE 0x00020000
291#define MIPS3_SR_DIAG_PE 0x00010000
292#define MIPS3_SR_KX 0x00000080
293#define MIPS3_SR_SX 0x00000040
294#define MIPS3_SR_UX 0x00000020
295#define MIPS3_SR_KSU_MASK 0x00000018
296#define MIPS3_SR_KSU_USER 0x00000010
297#define MIPS3_SR_KSU_SUPER 0x00000008
298#define MIPS3_SR_KSU_KERNEL 0x00000000
299#define MIPS3_SR_ERL 0x00000004
300#define MIPS3_SR_EXL 0x00000002
301
302#define MIPS_SR_SOFT_RESET MIPS3_SR_SOFT_RESET
303#define MIPS_SR_DIAG_CH MIPS3_SR_DIAG_CH
304#define MIPS_SR_DIAG_CE MIPS3_SR_DIAG_CE
305#define MIPS_SR_DIAG_PE MIPS3_SR_DIAG_PE
306#define MIPS_SR_KX MIPS3_SR_KX
307#define MIPS_SR_SX MIPS3_SR_SX
308#define MIPS_SR_UX MIPS3_SR_UX
309
310#define MIPS_SR_KSU_MASK MIPS3_SR_KSU_MASK
311#define MIPS_SR_KSU_USER MIPS3_SR_KSU_USER
312#define MIPS_SR_KSU_SUPER MIPS3_SR_KSU_SUPER
313#define MIPS_SR_KSU_KERNEL MIPS3_SR_KSU_KERNEL
314#define MIPS_SR_ERL MIPS3_SR_ERL
315#define MIPS_SR_EXL MIPS3_SR_EXL
316
317
318/*
319 * The interrupt masks.
320 * If a bit in the mask is 1 then the interrupt is enabled (or pending).
321 */
322#define MIPS_INT_MASK 0xff00
323#define MIPS_INT_MASK_5 0x8000
324#define MIPS_INT_MASK_4 0x4000
325#define MIPS_INT_MASK_3 0x2000
326#define MIPS_INT_MASK_2 0x1000
327#define MIPS_INT_MASK_1 0x0800
328#define MIPS_INT_MASK_0 0x0400
329#define MIPS_HARD_INT_MASK 0xfc00
330#define MIPS_SOFT_INT_MASK_1 0x0200
331#define MIPS_SOFT_INT_MASK_0 0x0100
332#define MIPS_SOFT_INT_MASK 0x0300
333#define MIPS_INT_MASK_SHIFT 8
334
335/*
336 * mips3 CPUs have on-chip timer at INT_MASK_5. Each platform can
337 * choose to enable this interrupt.
338 */
339#if defined(MIPS3_ENABLE_CLOCK_INTR)
340#define MIPS3_INT_MASK MIPS_INT_MASK
341#define MIPS3_HARD_INT_MASK MIPS_HARD_INT_MASK
342#else
343#define MIPS3_INT_MASK (MIPS_INT_MASK & ~MIPS_INT_MASK_5)
344#define MIPS3_HARD_INT_MASK (MIPS_HARD_INT_MASK & ~MIPS_INT_MASK_5)
345#endif
346
347/*
348 * The bits in the context register.
349 */
350#define MIPS1_CNTXT_PTE_BASE 0xFFE00000
351#define MIPS1_CNTXT_BAD_VPN 0x001FFFFC
352
353#define MIPS3_CNTXT_PTE_BASE 0xFF800000
354#define MIPS3_CNTXT_BAD_VPN2 0x007FFFF0
355
356/*
357 * The bits in the MIPS3 config register.
358 *
359 * bit 0..5: R/W, Bit 6..31: R/O
360 */
361
362/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
363#define MIPS3_CONFIG_K0_MASK 0x00000007
364
365/*
366 * R/W Update on Store Conditional
367 * 0: Store Conditional uses coherency algorithm specified by TLB
368 * 1: Store Conditional uses cacheable coherent update on write
369 */
370#define MIPS3_CONFIG_CU 0x00000008
371
372#define MIPS3_CONFIG_DB 0x00000010 /* Primary D-cache line size */
373#define MIPS3_CONFIG_IB 0x00000020 /* Primary I-cache line size */
374#define MIPS3_CONFIG_CACHE_L1_LSIZE(config, bit) \
375 (((config) & (bit)) ? 32 : 16)
376
377#define MIPS3_CONFIG_DC_MASK 0x000001c0 /* Primary D-cache size */
378#define MIPS3_CONFIG_DC_SHIFT 6
379#define MIPS3_CONFIG_IC_MASK 0x00000e00 /* Primary I-cache size */
380#define MIPS3_CONFIG_IC_SHIFT 9
381#define MIPS3_CONFIG_C_DEFBASE 0x1000 /* default base 2^12 */
382
383/* Cache size mode indication: available only on Vr41xx CPUs */
384#define MIPS3_CONFIG_CS 0x00001000
385#define MIPS3_CONFIG_C_4100BASE 0x0400 /* base is 2^10 if CS=1 */
386#define MIPS3_CONFIG_CACHE_SIZE(config, mask, base, shift) \
387 ((base) << (((config) & (mask)) >> (shift)))
388
389/* External cache enable: Controls L2 for R5000/Rm527x and L3 for Rm7000 */
390#define MIPS3_CONFIG_SE 0x00001000
391
392/* Block ordering: 0: sequential, 1: sub-block */
393#define MIPS3_CONFIG_EB 0x00002000
394
395/* ECC mode - 0: ECC mode, 1: parity mode */
396#define MIPS3_CONFIG_EM 0x00004000
397
398/* BigEndianMem - 0: kernel and memory are little endian, 1: big endian */
399#define MIPS3_CONFIG_BE 0x00008000
400
401/* Dirty Shared coherency state - 0: enabled, 1: disabled */
402#define MIPS3_CONFIG_SM 0x00010000
403
404/* Secondary Cache - 0: present, 1: not present */
405#define MIPS3_CONFIG_SC 0x00020000
406
407/* System Port width - 0: 64-bit, 1: 32-bit (QED RM523x), 2,3: reserved */
408#define MIPS3_CONFIG_EW_MASK 0x000c0000
409#define MIPS3_CONFIG_EW_SHIFT 18
410
411/* Secondary Cache port width - 0: 128-bit data path to S-cache, 1: reserved */
412#define MIPS3_CONFIG_SW 0x00100000
413
414/* Split Secondary Cache Mode - 0: I/D mixed, 1: I/D separated by SCAddr(17) */
415#define MIPS3_CONFIG_SS 0x00200000
416
417/* Secondary Cache line size */
418#define MIPS3_CONFIG_SB_MASK 0x00c00000
419#define MIPS3_CONFIG_SB_SHIFT 22
420#define MIPS3_CONFIG_CACHE_L2_LSIZE(config) \
421 (0x10 << (((config) & MIPS3_CONFIG_SB_MASK) >> MIPS3_CONFIG_SB_SHIFT))
422
423/* Write back data rate */
424#define MIPS3_CONFIG_EP_MASK 0x0f000000
425#define MIPS3_CONFIG_EP_SHIFT 24
426
427/* System clock ratio - this value is CPU dependent */
428#define MIPS3_CONFIG_EC_MASK 0x70000000
429#define MIPS3_CONFIG_EC_SHIFT 28
430
431/* Master-Checker Mode - 1: enabled */
432#define MIPS3_CONFIG_CM 0x80000000
433
434/*
435 * The bits in the MIPS4 config register.
436 */
437
438/* kseg0 coherency algorithm - see MIPS3_TLB_ATTR values */
439#define MIPS4_CONFIG_K0_MASK MIPS3_CONFIG_K0_MASK
440#define MIPS4_CONFIG_DN_MASK 0x00000018 /* Device number */
441#define MIPS4_CONFIG_CT 0x00000020 /* CohPrcReqTar */
442#define MIPS4_CONFIG_PE 0x00000040 /* PreElmReq */
443#define MIPS4_CONFIG_PM_MASK 0x00000180 /* PreReqMax */
444#define MIPS4_CONFIG_EC_MASK 0x00001e00 /* SysClkDiv */
445#define MIPS4_CONFIG_SB 0x00002000 /* SCBlkSize */
446#define MIPS4_CONFIG_SK 0x00004000 /* SCColEn */
447#define MIPS4_CONFIG_BE 0x00008000 /* MemEnd */
448#define MIPS4_CONFIG_SS_MASK 0x00070000 /* SCSize */
449#define MIPS4_CONFIG_SC_MASK 0x00380000 /* SCClkDiv */
450#define MIPS4_CONFIG_RESERVED 0x03c00000 /* Reserved wired 0 */
451#define MIPS4_CONFIG_DC_MASK 0x1c000000 /* Primary D-Cache size */
452#define MIPS4_CONFIG_IC_MASK 0xe0000000 /* Primary I-Cache size */
453
454#define MIPS4_CONFIG_DC_SHIFT 26
455#define MIPS4_CONFIG_IC_SHIFT 29
456
457#define MIPS4_CONFIG_CACHE_SIZE(config, mask, base, shift) \
458 ((base) << (((config) & (mask)) >> (shift)))
459
460#define MIPS4_CONFIG_CACHE_L2_LSIZE(config) \
461 (((config) & MIPS4_CONFIG_SB) ? 128 : 64)
462
463/*
464 * Location of exception vectors.
465 *
466 * Common vectors: reset and UTLB miss.
467 */
468#define MIPS_RESET_EXC_VEC MIPS_PHYS_TO_KSEG1(0x1FC00000)
469#define MIPS_UTLB_MISS_EXC_VEC MIPS_PHYS_TO_KSEG0(0)
470
471/*
472 * MIPS-1 general exception vector (everything else)
473 */
474#define MIPS1_GEN_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080)
475
476/*
477 * MIPS-III exception vectors
478 */
479#define MIPS3_XTLB_MISS_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0080)
480#define MIPS3_CACHE_ERR_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0100)
481#define MIPS3_GEN_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0180)
482
483/*
484 * MIPS32/MIPS64 (and some MIPS3) dedicated interrupt vector.
485 */
486#define MIPS3_INTR_EXC_VEC MIPS_PHYS_TO_KSEG0(0x0200)
487
488/*
489 * Coprocessor 0 registers:
490 *
491 * v--- width for mips I,III,32,64
492 * (3=32bit, 6=64bit, i=impl dep)
493 * 0 MIPS_COP_0_TLB_INDEX 3333 TLB Index.
494 * 1 MIPS_COP_0_TLB_RANDOM 3333 TLB Random.
495 * 2 MIPS_COP_0_TLB_LOW 3... r3k TLB entry low.
496 * 2 MIPS_COP_0_TLB_LO0 .636 r4k TLB entry low.
497 * 3 MIPS_COP_0_TLB_LO1 .636 r4k TLB entry low, extended.
498 * 4 MIPS_COP_0_TLB_CONTEXT 3636 TLB Context.
499 * 4/2 MIPS_COP_0_USERLOCAL ..36 UserLocal.
500 * 5 MIPS_COP_0_TLB_PG_MASK .333 TLB Page Mask register.
501 * 5/1 MIPS_COP_0_PG_GRAIN ..33 PageGrain register.
502 * 5/5 MIPS_COP_0_PWBASE ..33 Page Walker Base register.
503 * 5/6 MIPS_COP_0_PWFIELD ..33 Page Walker Field register.
504 * 5/7 MIPS_COP_0_PWSIZE ..33 Page Walker Size register.
505 * 6 MIPS_COP_0_TLB_WIRED .333 Wired TLB number.
506 * 6/6 MIPS_COP_0_PWCTL ..33 Page Walker Control register.
507 * 6/6 MIPS_COP_0_EIRR ...6 [RMI] Extended Interrupt Request Register.
508 * 6/7 MIPS_COP_0_EIMR ...6 [RMI] Extended Interrupt Mask Register.
509 * 7 MIPS_COP_0_HWRENA ..33 rdHWR Enable.
510 * 8 MIPS_COP_0_BAD_VADDR 3636 Bad virtual address.
511 * 9 MIPS_COP_0_COUNT .333 Count register.
512 * 9/6 MIPS_COP_0_CVMCNT ...6 [CAVIUM] CvmCtl register.
513 * 9/7 MIPS_COP_0_CVMCTL ...6 [CAVIUM] CvmCount register (64 bit).
514 * 10 MIPS_COP_0_TLB_HI 3636 TLB entry high.
515 * 11 MIPS_COP_0_COMPARE .333 Compare (against Count).
516 * 11/7 MIPS_COP_0_CVMMEMCTL ...6 [CAVIUM] CvmMemCtl register.
517 * 12 MIPS_COP_0_STATUS 3333 Status register.
518 * 12/1 MIPS_COP_0_INTCTL ..33 Interrupt Control.
519 * 12/2 MIPS_COP_0_SRSCTL ..33 Shadow Register Set Selectors.
520 * 12/3 MIPS_COP_0_SRSMAP ..33 Shadow Set Map.
521 * 13 MIPS_COP_0_CAUSE 3333 Exception cause register.
522 * 14 MIPS_COP_0_EXC_PC 3636 Exception PC.
523 * 15 MIPS_COP_0_PRID 3333 Processor revision identifier.
524 * 15/1 MIPS_COP_0_EBASE ..33 Exception Base.
525 * 16 MIPS_COP_0_CONFIG 3333 Configuration register.
526 * 16/1 MIPS_COP_0_CONFIG1 ..33 Configuration register 1.
527 * 16/2 MIPS_COP_0_CONFIG2 ..33 Configuration register 2.
528 * 16/3 MIPS_COP_0_CONFIG3 ..33 Configuration register 3.
529 * 16/4 MIPS_COP_0_CONFIG4 ..33 Configuration register 6.
530 * 16/5 MIPS_COP_0_CONFIG5 ..33 Configuration register 7.
531 * 16/6 MIPS_COP_0_CONFIG6 ..33 Configuration register 6.
532 * 16/6 MIPS_COP_0_CVMMEMCTL2 ...6 [CAVIUM] CvmMemCtl2 register.
533 * 16/7 MIPS_COP_0_CONFIG7 ..33 Configuration register 7.
534 * 16/7 MIPS_COP_0_CVMVMCONFIG ...6 [CAVIUM] CvmVMConfig register.
535 * 17 MIPS_COP_0_LLADDR .336 Load Linked Address.
536 * 18 MIPS_COP_0_WATCH_LO .336 WatchLo register.
537 * 18/1 MIPS_COP_0_WATCH_LO2 ..ii WatchLo 1 register.
538 * 19 MIPS_COP_0_WATCH_HI .333 WatchHi register.
539 * 19/1 MIPS_COP_0_WATCH_HI1 ..ii WatchHi 1 register.
540 * 20 MIPS_COP_0_TLB_XCONTEXT .6.6 TLB XContext register.
541 * 22 MIPS_COP_0_OSSCRATCH ...6 [RMI] OS Scratch register. (select 0..7)
542 * 22 MIPS_COP_0_DIAG ...6 [LOONGSON2] Diagnostic register.
543 * 22 MIPS_COP_0_MCD ...6 [CAVIUM] Multi-Core Debug register.
544 * 23 MIPS_COP_0_DEBUG .... Debug JTAG register.
545 * 24 MIPS_COP_0_DEPC .... DEPC JTAG register.
546 * 25/0 MIPS_COP_0_PERFCNT0_CTL ..ii Performance Counter 0 control register.
547 * 25/1 MIPS_COP_0_PERFCNT0_CNT ..ii Performance Counter 0 value register.
548 * 25/2 MIPS_COP_0_PERFCNT1_CTL ..ii Performance Counter 1 control register.
549 * 25/3 MIPS_COP_0_PERFCNT1_CNT ..ii Performance Counter 1 value register.
550 * 25/4 MIPS_COP_0_PERFCNT0_CTL ..ii Performance Counter 2 control register.
551 * 25/5 MIPS_COP_0_PERFCNT0_CNT ..ii Performance Counter 2 value register.
552 * 25/6 MIPS_COP_0_PERFCNT1_CTL ..ii Performance Counter 3 control register.
553 * 25/7 MIPS_COP_0_PERFCNT1_CNT ..ii Performance Counter 3 value register.
554 * 26 MIPS_COP_0_ECC .3ii ECC / Error Control register.
555 * 27 MIPS_COP_0_CACHE_ERR .3ii Cache Error register.
556 * 27 MIPS_COP_0_CACHE_ERR_I ...6 [CAVIUM] Cache Error register (instr).
557 * 27/1 MIPS_COP_0_CACHE_ERR_D ...6 [CAVIUM] Cache Error register (data).
558 * 27/1 MIPS_COP_0_CACHE_ERR .3ii Cache Error register.
559 * 28/0 MIPS_COP_0_TAG_LO .3ii Cache TagLo register (instr).
560 * 28/1 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (instr).
561 * 28/2 MIPS_COP_0_TAG_LO ..ii Cache TagLo register (data).
562 * 28/3 MIPS_COP_0_DATA_LO ..ii Cache DataLo register (data).
563 * 29/0 MIPS_COP_0_TAG_HI .3ii Cache TagHi register (instr).
564 * 29/1 MIPS_COP_0_DATA_HI ..ii Cache DataHi register (instr).
565 * 29/2 MIPS_COP_0_TAG_HI_DATA ..ii Cache TagHi register (data).
566 * 29/3 MIPS_COP_0_DATA_HI_DATA ..ii Cache DataHi register (data).
567 * 30 MIPS_COP_0_ERROR_PC .636 Error EPC register.
568 * 31 MIPS_COP_0_DESAVE .... DESAVE JTAG register.
569 */
570#ifdef _LOCORE
571#define _(n) __CONCAT($,n)
572#else
573#define _(n) n
574#endif
575#define MIPS_COP_0_TLB_INDEX _(0)
576#define MIPS_COP_0_TLB_RANDOM _(1)
577 /* Name and meaning of TLB bits for $2 differ on r3k and r4k. */
578
579#define MIPS_COP_0_TLB_CONTEXT _(4)
580 /* $5 and $6 new with MIPS-III */
581#define MIPS_COP_0_BAD_VADDR _(8)
582#define MIPS_COP_0_TLB_HI _(10)
583#define MIPS_COP_0_STATUS _(12)
584#define MIPS_COP_0_CAUSE _(13)
585#define MIPS_COP_0_EXC_PC _(14)
586#define MIPS_COP_0_PRID _(15)
587
588/* MIPS-I */
589#define MIPS_COP_0_TLB_LOW _(2)
590
591/* MIPS-III */
592#define MIPS_COP_0_TLB_LO0 _(2)
593#define MIPS_COP_0_TLB_LO1 _(3)
594
595#define MIPS_COP_0_TLB_PG_MASK _(5)
596#define MIPS_COP_0_TLB_WIRED _(6)
597
598#define MIPS_COP_0_COUNT _(9)
599#define MIPS_COP_0_COMPARE _(11)
600
601#define MIPS_COP_0_CONFIG _(16)
602#define MIPS_COP_0_LLADDR _(17)
603#define MIPS_COP_0_WATCH_LO _(18)
604#define MIPS_COP_0_WATCH_LO1 _(18), 1 /* MIPS32/64 optional */
605#define MIPS_COP_0_WATCH_HI _(19)
606#define MIPS_COP_0_WATCH_HI1 _(19), 1 /* MIPS32/64 optional */
607#define MIPS_COP_0_TLB_XCONTEXT _(20)
608#define MIPS_COP_0_ECC _(26)
609#define MIPS_COP_0_CACHE_ERR _(27)
610#define MIPS_COP_0_CACHE_ERR_I _(27) /* CAVIUM */
611#define MIPS_COP_0_CACHE_ERR_D _(27), 1 /* CAVIUM */
612#define MIPS_COP_0_TAG_LO _(28)
613#define MIPS_COP_0_TAG_HI _(29)
614#define MIPS_COP_0_TAG_HI_DATA _(29), 2
615#define MIPS_COP_0_ERROR_PC _(30)
616
617/* MIPS32/64 */
618#define MIPS_COP_0_CTXCONFIG _(4), 1
619#define MIPS_COP_0_USERLOCAL _(4), 2
620#define MIPS_COP_0_XCTXCONFIG _(4), 3 /* MIPS64 */
621#define MIPS_COP_0_PGGRAIN _(5), 1
622#define MIPS_COP_0_SEGCTL0 _(5), 2
623#define MIPS_COP_0_SEGCTL1 _(5), 3
624#define MIPS_COP_0_SEGCTL2 _(5), 4
625#define MIPS_COP_0_PWBASE _(5), 5
626#define MIPS_COP_0_PWFIELD _(5), 6
627#define MIPS_COP_0_PWSIZE _(5), 7
628#define MIPS_COP_0_PWCTL _(6), 6
629#define MIPS_COP_0_EIRR _(6), 6 /* RMI */
630#define MIPS_COP_0_EIMR _(6), 7 /* RMI */
631#define MIPS_COP_0_HWRENA _(7)
632#define MIPS_COP_0_BADINSTR _(8), 1
633#define MIPS_COP_0_BADINSTRP _(8), 2
634#define MIPS_COP_0_CVMCNT _(9), 6 /* CAVIUM */
635#define MIPS_COP_0_CVMCTL _(9), 7 /* CAVIUM */
636#define MIPS_COP_0_CVMMEMCTL _(11), 7 /* CAVIUM */
637#define MIPS_COP_0_INTCTL _(12), 1
638#define MIPS_COP_0_SRSCTL _(12), 2
639#define MIPS_COP_0_SRSMAP _(12), 3
640#define MIPS_COP_0_NESTEDEXC _(13), 5
641#define MIPS_COP_0_NESTED_EPC _(14), 2
642#define MIPS_COP_0_EBASE _(15), 1
643#define MIPS_COP_0_CDMMBASE _(15), 2
644#define MIPS_COP_0_CMGCRBASE _(15), 3
645#define MIPS_COP_0_CONFIG1 _(16), 1
646#define MIPS_COP_0_CONFIG2 _(16), 2
647#define MIPS_COP_0_CONFIG3 _(16), 3
648#define MIPS_COP_0_CONFIG4 _(16), 4
649#define MIPS_COP_0_CONFIG5 _(16), 5
650#define MIPS_COP_0_CONFIG6 _(16), 6
651#define MIPS_COP_0_CVMMEMCTL2 _(16), 6 /* CAVIUM */
652#define MIPS_COP_0_CONFIG7 _(16), 7
653#define MIPS_COP_0_CVMVMCONFIG _(16), 7 /* CAVIUM */
654#define MIPS_COP_0_OSSCRATCH _(22) /* RMI */
655#define MIPS_COP_0_DIAG _(22) /* LOONGSON2 */
656#define MIPS_COP_0_MCD _(22) /* CAVIUM */
657#define MIPS_COP_0_DEBUG _(23)
658#define MIPS_COP_0_DEPC _(24)
659#define MIPS_COP_0_PERFCNT0_CTL _(25)
660#define MIPS_COP_0_PERFCNT0_CNT _(25), 1
661#define MIPS_COP_0_PERFCNT1_CTL _(25), 2
662#define MIPS_COP_0_PERFCNT1_CNT _(25), 3
663#define MIPS_COP_0_PERFCNT2_CTL _(25), 4
664#define MIPS_COP_0_PERFCNT2_CNT _(25), 5
665#define MIPS_COP_0_PERFCNT3_CTL _(25), 6
666#define MIPS_COP_0_PERFCNT3_CNT _(25), 7
667#define MIPS_COP_0_DATA_LO _(28), 1
668#define MIPS_COP_0_DATA_HI _(29), 3
669#define MIPS_COP_0_DATA_HI_DATA _(29)
670#define MIPS_COP_0_DESAVE _(31)
671
672#define MIPS_DIAG_RAS_DISABLE 0x00000001 /* Loongson2 */
673#define MIPS_DIAG_BTB_CLEAR 0x00000002 /* Loongson2 */
674#define MIPS_DIAG_ITLB_CLEAR 0x00000004 /* Loongson2 */
675
676/*
677 * Values for the code field in a break instruction.
678 */
679#define MIPS_BREAK_INSTR 0x0000000d
680#define MIPS_BREAK_VAL_MASK 0x03ff0000
681#define MIPS_BREAK_VAL_SHIFT 16
682#define MIPS_BREAK_INTOVERFLOW 6 /* used by gas to indicate int overflow */
683#define MIPS_BREAK_INTDIVZERO 7 /* used by gas/gcc to indicate int div by zero */
684#define MIPS_BREAK_KDB_VAL 512
685#define MIPS_BREAK_SSTEP_VAL 513
686#define MIPS_BREAK_BRKPT_VAL 514
687#define MIPS_BREAK_SOVER_VAL 515
688#define MIPS_BREAK_KDB (MIPS_BREAK_INSTR | \
689 (MIPS_BREAK_KDB_VAL << MIPS_BREAK_VAL_SHIFT))
690#define MIPS_BREAK_SSTEP (MIPS_BREAK_INSTR | \
691 (MIPS_BREAK_SSTEP_VAL << MIPS_BREAK_VAL_SHIFT))
692#define MIPS_BREAK_BRKPT (MIPS_BREAK_INSTR | \
693 (MIPS_BREAK_BRKPT_VAL << MIPS_BREAK_VAL_SHIFT))
694#define MIPS_BREAK_SOVER (MIPS_BREAK_INSTR | \
695 (MIPS_BREAK_SOVER_VAL << MIPS_BREAK_VAL_SHIFT))
696
697/*
698 * Minimum and maximum cache sizes.
699 */
700#define MIPS_MIN_CACHE_SIZE (16 * 1024)
701#define MIPS_MAX_CACHE_SIZE (256 * 1024)
702#define MIPS3_MAX_PCACHE_SIZE (32 * 1024) /* max. primary cache size */
703
704/*
705 * The floating point version and status registers.
706 */
707#define MIPS_FIR $0 /* FP Implementation and Revision Register */
708#define MIPS_FCSR $31 /* FP Control/Status Register */
709
710/*
711 * The floating point coprocessor status register bits.
712 */
713#define MIPS_FCSR_RM __BITS(1,0)
714#define MIPS_FCSR_RM_RN 0 /* round to nearest */
715#define MIPS_FCSR_RM_RZ 1 /* round towards zero */
716#define MIPS_FCSR_RM_RP 2 /* round towards +infinity */
717#define MIPS_FCSR_RM_RM 3 /* round towards -infinity */
718#define MIPS_FCSR_FLAGS __BITS(6,2)
719#define MIPS_FCSR_FLAGS_I __BIT(2) /* inexact */
720#define MIPS_FCSR_FLAGS_U __BIT(3) /* underflow */
721#define MIPS_FCSR_FLAGS_O __BIT(4) /* overflow */
722#define MIPS_FCSR_FLAGS_Z __BIT(5) /* divide by zero */
723#define MIPS_FCSR_FLAGS_V __BIT(6) /* invalid operation */
724#define MIPS_FCSR_ENABLES __BITS(11,7)
725#define MIPS_FCSR_ENABLES_I __BIT(7) /* inexact */
726#define MIPS_FCSR_ENABLES_U __BIT(8) /* underflow */
727#define MIPS_FCSR_ENABLES_O __BIT(9) /* overflow */
728#define MIPS_FCSR_ENABLES_Z __BIT(10) /* divide by zero */
729#define MIPS_FCSR_ENABLES_V __BIT(11) /* invalid operation */
730#define MIPS_FCSR_CAUSE __BITS(17,12)
731#define MIPS_FCSR_CAUSE_I __BIT(12) /* inexact */
732#define MIPS_FCSR_CAUSE_U __BIT(13) /* underflow */
733#define MIPS_FCSR_CAUSE_O __BIT(14) /* overflow */
734#define MIPS_FCSR_CAUSE_Z __BIT(15) /* divide by zero */
735#define MIPS_FCSR_CAUSE_V __BIT(16) /* invalid operation */
736#define MIPS_FCSR_CAUSE_E __BIT(17) /* unimplemented operation */
737#define MIPS_FCSR_NAN_2008 __BIT(18)
738#define MIPS_FCSR_ABS_2008 __BIT(19)
739#define MIPS_FCSR_FCC0 __BIT(23)
740#define MIPS_FCSR_FCC (MIPS_FPU_COND_BIT | __BITS(31,25))
741#define MIPS_FCSR_FS __BIT(24) /* r4k+ */
742
743
744/*
745 * Constants to determine if have a floating point instruction.
746 */
747#define MIPS_OPCODE_SHIFT 26
748#define MIPS_OPCODE_C1 0x11
749
750
751/*
752 * The low part of the TLB entry.
753 */
754#define MIPS1_TLB_PFN 0xfffff000
755#define MIPS1_TLB_NON_CACHEABLE_BIT 0x00000800
756#define MIPS1_TLB_DIRTY_BIT 0x00000400
757#define MIPS1_TLB_VALID_BIT 0x00000200
758#define MIPS1_TLB_GLOBAL_BIT 0x00000100
759
760#define MIPS3_TLB_PFN 0x3fffffc0
761#define MIPS3_TLB_ATTR_MASK 0x00000038
762#define MIPS3_TLB_ATTR_SHIFT 3
763#define MIPS3_TLB_DIRTY_BIT 0x00000004
764#define MIPS3_TLB_VALID_BIT 0x00000002
765#define MIPS3_TLB_GLOBAL_BIT 0x00000001
766
767#define MIPS1_TLB_PHYS_PAGE_SHIFT 12
768#define MIPS3_TLB_PHYS_PAGE_SHIFT 6
769#define MIPS1_TLB_PF_NUM MIPS1_TLB_PFN
770#define MIPS3_TLB_PF_NUM MIPS3_TLB_PFN
771#define MIPS1_TLB_MOD_BIT MIPS1_TLB_DIRTY_BIT
772#define MIPS3_TLB_MOD_BIT MIPS3_TLB_DIRTY_BIT
773
774/*
775 * MIPS3_TLB_ATTR (CCA) values - coherency algorithm:
776 * 0: cacheable, noncoherent, write-through, no write allocate
777 * 1: cacheable, noncoherent, write-through, write allocate
778 * 2: uncached
779 * 3: cacheable, noncoherent, write-back (noncoherent)
780 * 4: cacheable, coherent, write-back, exclusive (exclusive)
781 * 5: cacheable, coherent, write-back, exclusive on write (sharable)
782 * 6: cacheable, coherent, write-back, update on write (update)
783 * 7: uncached, accelerated (gather STORE operations)
784 */
785#define MIPS3_TLB_ATTR_WT 0 /* IDT */
786#define MIPS3_TLB_ATTR_WT_WRITEALLOCATE 1 /* IDT */
787#define MIPS3_TLB_ATTR_UNCACHED 2 /* R4000/R4400, IDT */
788#define MIPS3_TLB_ATTR_WB_NONCOHERENT 3 /* R4000/R4400, IDT */
789#define MIPS3_TLB_ATTR_WB_EXCLUSIVE 4 /* R4000/R4400 */
790#define MIPS3_TLB_ATTR_WB_SHARABLE 5 /* R4000/R4400 */
791#define MIPS3_TLB_ATTR_WB_UPDATE 6 /* R4000/R4400 */
792#define MIPS4_TLB_ATTR_UNCACHED_ACCELERATED 7 /* R10000 */
793
794
795/*
796 * The high part of the TLB entry.
797 */
798#define MIPS1_TLB_VPN 0xfffff000
799#define MIPS1_TLB_PID 0x00000fc0
800#define MIPS1_TLB_PID_SHIFT 6
801
802#define MIPS3_TLB_VPN2 0xffffe000
803#define MIPS3_TLB_EHINV 0x00000400 /* mipsNN R3 */
804#define MIPS3_TLB_ASID 0x000000ff
805
806#define MIPS1_TLB_VIRT_PAGE_NUM MIPS1_TLB_VPN
807#define MIPS3_TLB_VIRT_PAGE_NUM MIPS3_TLB_VPN2
808#define MIPS3_TLB_PID MIPS3_TLB_ASID
809#define MIPS_TLB_VIRT_PAGE_SHIFT 12
810
811/*
812 * r3000: shift count to put the index in the right spot.
813 */
814#define MIPS1_TLB_INDEX_SHIFT 8
815
816/*
817 * The first TLB that write random hits.
818 */
819#define MIPS1_TLB_FIRST_RAND_ENTRY 8
820#define MIPS3_TLB_WIRED_UPAGES 1
821
822/*
823 * The number of process id entries.
824 */
825#define MIPS1_TLB_NUM_PIDS 64
826#define MIPS3_TLB_NUM_ASIDS 256
827
828/*
829 * Patch codes to hide CPU design differences between MIPS1 and MIPS3.
830 */
831
832/* XXX simonb: this is before MIPS3_PLUS is defined (and is ugly!) */
833
834#if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) == 0 && MIPS1 != 0
835#define MIPS_TLB_PID_SHIFT MIPS1_TLB_PID_SHIFT
836#define MIPS_TLB_PID MIPS1_TLB_PID
837#define MIPS_TLB_NUM_PIDS MIPS1_TLB_NUM_PIDS
838#endif
839
840#if (MIPS3 + MIPS4 + MIPS32 + MIPS32R2 + MIPS64 + MIPS64R2) != 0 && MIPS1 == 0
841#define MIPS_TLB_PID_SHIFT 0
842#define MIPS_TLB_PID MIPS3_TLB_PID
843#define MIPS_TLB_NUM_PIDS MIPS3_TLB_NUM_ASIDS
844#endif
845
846
847#if !defined(MIPS_TLB_PID_SHIFT)
848#define MIPS_TLB_PID_SHIFT \
849 ((MIPS_HAS_R4K_MMU) ? 0 : MIPS1_TLB_PID_SHIFT)
850
851#define MIPS_TLB_PID \
852 ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_PID : MIPS1_TLB_PID)
853
854#define MIPS_TLB_NUM_PIDS \
855 ((MIPS_HAS_R4K_MMU) ? MIPS3_TLB_NUM_ASIDS : MIPS1_TLB_NUM_PIDS)
856#endif
857
858/*
859 * WatchLo/WatchHi watchpoint registers
860 */
861#define MIPS_WATCHLO_VADDR32 __BITS(31,3) /* 32-bit addr */
862#define MIPS_WATCHLO_VADDR64 __BITS(63,3) /* 64-bit addr */
863#define MIPS_WATCHLO_INSN __BIT(2)
864#define MIPS_WATCHLO_DATA_READ __BIT(1)
865#define MIPS_WATCHLO_DATA_WRITE __BIT(0)
866
867#define MIPS_WATCHHI_M __BIT(31) /* next watch reg implemented */
868#define MIPS_WATCHHI_G __BIT(30) /* use WatchLo vaddr */
869#define MIPS_WATCHHI_EAS __BITS(25,24) /* extended ASID */
870#define MIPS_WATCHHI_ASID __BITS(23,16)
871#define MIPS_WATCHHI_MASK __BITS(11,3)
872#define MIPS_WATCHHI_INSN MIPS_WATCHLO_INSN
873#define MIPS_WATCHHI_DATA_READ MIPS_WATCHLO_DATA_READ
874#define MIPS_WATCHHI_DATA_WRITE MIPS_WATCHLO_DATA_WRITE
875
876/*
877 * RDHWR register numbers
878 */
879#define MIPS_HWR_CPUNUM _(0) /* Which CPU are we on? */
880#define MIPS_HWR_SYNCI_STEP _(1) /* Address step size for SYNCI */
881#define MIPS_HWR_CC _(2) /* Hi-res cycle counter */
882#define MIPS_HWR_CCRES _(3) /* Cycle counter resolution */
883#define MIPS_HWR_ULR _(29) /* Userlocal */
884#define MIPS_HWR_IMPL30 _(30) /* Implementation dependent use */
885#define MIPS_HWR_IMPL31 _(31) /* Implementation dependent use */
886
887/*
888 * Bits defined for HWREna (CP0 register 7, select 0).
889 */
890#define MIPS_HWRENA_IMPL31 __BIT(MIPS_HWR_IMPL31)
891#define MIPS_HWRENA_IMPL30 __BIT(MIPS_HWR_IMPL30)
892#define MIPS_HWRENA_ULR __BIT(MIPS_HWR_ULR)
893#define MIPS_HWRENA_CCRES __BIT(MIPS_HWR_CCRES)
894#define MIPS_HWRENA_CC __BIT(MIPS_HWR_CC)
895#define MIPS_HWRENA_SYNCI_STEP __BIT(MIPS_HWR_SYNCI_STEP)
896#define MIPS_HWRENA_CPUNUM __BIT(MIPS_HWR_CPUNUM)
897
898/*
899 * Bits defined for EBASE (CP0 register 15, select 1).
900 */
901#define MIPS_EBASE_EXC_BASE_SHIFT 12
902#define MIPS_EBASE_EXC_BASE __BITS(29, MIPS_EBASE_EXC_BASE_SHIFT)
903#define MIPS_EBASE_CPUNUM __BITS(9, 0)
904#define MIPS_EBASE_CPUNUM_WIDTH 10 /* used by asm code */
905
906/*
907 * Hints for the prefetch instruction
908 */
909
910/*
911 * Prefetched data is expected to be read (not modified)
912 */
913#define PREF_LOAD 0
914#define PREF_LOAD_STREAMED 4 /* but not reused extensively; it */
915 /* "streams" through cache. */
916#define PREF_LOAD_RETAINED 6 /* and reused extensively; it should */
917 /* be "retained" in the cache. */
918
919/*
920 * Prefetched data is expected to be stored or modified
921 */
922#define PREF_STORE 1
923#define PREF_STORE_STREAMED 5 /* but not reused extensively; it */
924 /* "streams" through cache. */
925#define PREF_STORE_RETAINED 7 /* and reused extensively; it should */
926 /* be "retained" in the cache. */
927
928/*
929 * data is no longer expected to be used. For a WB cache, schedule a
930 * writeback of any dirty data and afterwards free the cache lines.
931 */
932#define PREF_WB_INV 25
933#define PREF_NUDGE PREF_WB_INV
934
935/*
936 * Prepare for writing an entire cache line without the overhead
937 * involved in filling the line from memory.
938 */
939#define PREF_PREPAREFORSTORE 30
940
941/*
942 * CPU processor revision IDs for company ID == 0 (non mips32/64 chips)
943 */
944#define MIPS_R2000 0x01 /* MIPS R2000 ISA I */
945#define MIPS_R3000 0x02 /* MIPS R3000 ISA I */
946#define MIPS_R6000 0x03 /* MIPS R6000 ISA II */
947#define MIPS_R4000 0x04 /* MIPS R4000/R4400 ISA III */
948#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivative ISA I */
949#define MIPS_R6000A 0x06 /* MIPS R6000A ISA II */
950#define MIPS_R3IDT 0x07 /* IDT R3041 or RC36100 ISA I */
951#define MIPS_R10000 0x09 /* MIPS R10000 ISA IV */
952#define MIPS_R4200 0x0a /* NEC VR4200 ISA III */
953#define MIPS_R4300 0x0b /* NEC VR4300 ISA III */
954#define MIPS_R4100 0x0c /* NEC VR4100 ISA III */
955#define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */
956#define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */
957#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
958#define MIPS_RC32300 0x18 /* IDT RC32334,332,355 ISA 32 */
959#define MIPS_R4600 0x20 /* QED R4600 Orion ISA III */
960#define MIPS_R4700 0x21 /* QED R4700 Orion ISA III */
961#define MIPS_R3SONY 0x21 /* Sony R3000 based ISA I */
962#define MIPS_R4650 0x22 /* QED R4650 ISA III */
963#define MIPS_TX3900 0x22 /* Toshiba TX39 family ISA I */
964#define MIPS_R5000 0x23 /* MIPS R5000 ISA IV */
965#define MIPS_R3NKK 0x23 /* NKK R3000 based ISA I */
966#define MIPS_RC32364 0x26 /* IDT RC32364 ISA 32 */
967#define MIPS_RM7000 0x27 /* QED RM7000 ISA IV */
968#define MIPS_RM5200 0x28 /* QED RM5200s ISA IV */
969#define MIPS_TX4900 0x2d /* Toshiba TX49 family ISA III */
970#define MIPS_R5900 0x2e /* Toshiba R5900 (EECore) ISA --- */
971#define MIPS_RC64470 0x30 /* IDT RC64474/RC64475 ISA III */
972#define MIPS_TX7900 0x38 /* Toshiba TX79 ISA III+*/
973#define MIPS_R5400 0x54 /* NEC VR5400 ISA IV */
974#define MIPS_R5500 0x55 /* NEC VR5500 ISA IV */
975#define MIPS_LOONGSON2 0x63 /* ICT Loongson-2 ISA III */
976
977/*
978 * CPU revision IDs for some prehistoric processors.
979 */
980
981/* For MIPS_R3000 */
982#define MIPS_REV_R2000A 0x16 /* R2000A uses R3000 proc revision */
983#define MIPS_REV_R3000 0x20
984#define MIPS_REV_R3000A 0x30
985
986/* For MIPS_TX3900 */
987#define MIPS_REV_TX3912 0x10
988#define MIPS_REV_TX3922 0x30
989#define MIPS_REV_TX3927 0x40
990
991/* For MIPS_R4000 */
992#define MIPS_REV_R4000_A 0x00
993#define MIPS_REV_R4000_B 0x22
994#define MIPS_REV_R4000_C 0x30
995#define MIPS_REV_R4400_A 0x40
996#define MIPS_REV_R4400_B 0x50
997#define MIPS_REV_R4400_C 0x60
998
999/* For MIPS_TX4900 */
1000#define MIPS_REV_TX4927 0x22
1001
1002/* For MIPS_LOONGSON2 */
1003#define MIPS_REV_LOONGSON2E 0x02
1004#define MIPS_REV_LOONGSON2F 0x03
1005
1006/*
1007 * CPU processor revision IDs for company ID == 1 (MIPS)
1008 */
1009#define MIPS_4Kc 0x80 /* MIPS 4Kc ISA 32 */
1010#define MIPS_5Kc 0x81 /* MIPS 5Kc ISA 64 */
1011#define MIPS_20Kc 0x82 /* MIPS 20Kc ISA 64 */
1012#define MIPS_4Kmp 0x83 /* MIPS 4Km/4Kp ISA 32 */
1013#define MIPS_4KEc 0x84 /* MIPS 4KEc ISA 32 */
1014#define MIPS_4KEmp 0x85 /* MIPS 4KEm/4KEp ISA 32 */
1015#define MIPS_4KSc 0x86 /* MIPS 4KSc ISA 32 */
1016#define MIPS_M4K 0x87 /* MIPS M4K ISA 32 Rel 2 */
1017#define MIPS_25Kf 0x88 /* MIPS 25Kf ISA 64 */
1018#define MIPS_5KE 0x89 /* MIPS 5KE ISA 64 Rel 2 */
1019#define MIPS_4KEc_R2 0x90 /* MIPS 4KEc_R2 ISA 32 Rel 2 */
1020#define MIPS_4KEmp_R2 0x91 /* MIPS 4KEm/4KEp_R2 ISA 32 Rel 2 */
1021#define MIPS_4KSd 0x92 /* MIPS 4KSd ISA 32 Rel 2 */
1022#define MIPS_24K 0x93 /* MIPS 24Kc/24Kf ISA 32 Rel 2 */
1023#define MIPS_34K 0x95 /* MIPS 34K ISA 32 R2 MT */
1024#define MIPS_24KE 0x96 /* MIPS 24KEc ISA 32 Rel 2 */
1025#define MIPS_74K 0x97 /* MIPS 74Kc/74Kf ISA 32 Rel 2 */
1026#define MIPS_1004K 0x99 /* MIPS 1004Kc/1004Kf ISA 32 Rel 2 */
1027#define MIPS_1074K 0x9a /* MIPS 1074Kc/1074Kf ISA 32 Rel 2 */
1028#define MIPS_interAptiv 0xa1 /* MIPS interAptiv ISA 32 R3 MT */
1029
1030/*
1031 * CPU processor revision IDs for company ID == 2 (Broadcom)
1032 */
1033#define MIPS_BCM3302 0x90 /* MIPS 4KEc_R2-like? ISA 32 Rel 2 */
1034
1035/*
1036 * Alchemy (company ID 3) use the processor ID field to denote the CPU core
1037 * revision and the company options field do donate the SOC chip type.
1038 */
1039/* CPU processor revision IDs */
1040#define MIPS_AU_REV1 0x01 /* Alchemy Au1000 (Rev 1) ISA 32 */
1041#define MIPS_AU_REV2 0x02 /* Alchemy Au1000 (Rev 2) ISA 32 */
1042/* CPU company options IDs */
1043#define MIPS_AU1000 0x00
1044#define MIPS_AU1500 0x01
1045#define MIPS_AU1100 0x02
1046#define MIPS_AU1550 0x03
1047
1048/*
1049 * CPU processor revision IDs for company ID == 4 (SiByte)
1050 */
1051#define MIPS_SB1 0x01 /* SiByte SB1 ISA 64 */
1052#define MIPS_SB1_11 0x11 /* SiByte SB1 (rev 0x11) ISA 64 */
1053
1054/*
1055 * CPU processor revision IDs for company ID == 5 (SandCraft)
1056 */
1057#define MIPS_SR7100 0x04 /* SandCraft SR7100 ISA 64 */
1058
1059/*
1060 * CPU revision IDs for company ID == 12 (RMI)
1061 * note: unlisted Rev values may indicate pre-production silicon
1062 */
1063#define MIPS_XLR_B2 0x04 /* RMI XLR Production Rev B2 */
1064#define MIPS_XLR_C4 0x91 /* RMI XLR Production Rev C4 */
1065
1066/*
1067 * CPU processor IDs for company ID == 12 (RMI)
1068 */
1069#define MIPS_XLR308B 0x06 /* RMI XLR308-B ISA 64 */
1070#define MIPS_XLR508B 0x07 /* RMI XLR508-B ISA 64 */
1071#define MIPS_XLR516B 0x08 /* RMI XLR516-B ISA 64 */
1072#define MIPS_XLR532B 0x09 /* RMI XLR532-B ISA 64 */
1073#define MIPS_XLR716B 0x0a /* RMI XLR716-B ISA 64 */
1074#define MIPS_XLR732B 0x0b /* RMI XLR732-B ISA 64 */
1075#define MIPS_XLR732C 0x00 /* RMI XLR732-C ISA 64 */
1076#define MIPS_XLR716C 0x02 /* RMI XLR716-C ISA 64 */
1077#define MIPS_XLR532C 0x08 /* RMI XLR532-C ISA 64 */
1078#define MIPS_XLR516C 0x0a /* RMI XLR516-C ISA 64 */
1079#define MIPS_XLR508C 0x0b /* RMI XLR508-C ISA 64 */
1080#define MIPS_XLR308C 0x0f /* RMI XLR308-C ISA 64 */
1081#define MIPS_XLS616 0x40 /* RMI XLS616 ISA 64 */
1082#define MIPS_XLS416 0x44 /* RMI XLS416 ISA 64 */
1083#define MIPS_XLS608 0x4A /* RMI XLS608 ISA 64 */
1084#define MIPS_XLS408 0x4E /* RMI XLS406 ISA 64 */
1085#define MIPS_XLS404 0x4F /* RMI XLS404 ISA 64 */
1086#define MIPS_XLS408LITE 0x88 /* RMI XLS408-Lite ISA 64 */
1087#define MIPS_XLS404LITE 0x8C /* RMI XLS404-Lite ISA 64 */
1088#define MIPS_XLS208 0x8E /* RMI XLS208 ISA 64 */
1089#define MIPS_XLS204 0x8F /* RMI XLS204 ISA 64 */
1090#define MIPS_XLS108 0xCE /* RMI XLS108 ISA 64 */
1091#define MIPS_XLS104 0xCF /* RMI XLS104 ISA 64 */
1092
1093/*
1094 * CPU processor IDs for company ID == 13 (Cavium)
1095 */
1096#define MIPS_CN38XX 0x00 /* Cavium Octeon CN38XX ISA 64 */
1097#define MIPS_CN31XX 0x01 /* Cavium Octeon CN31XX ISA 64 */
1098#define MIPS_CN30XX 0x02 /* Cavium Octeon CN30XX ISA 64 */
1099#define MIPS_CN58XX 0x03 /* Cavium Octeon CN58XX ISA 64 */
1100#define MIPS_CN56XX 0x04 /* Cavium Octeon CN56XX ISA 64 */
1101#define MIPS_CN50XX 0x06 /* Cavium Octeon CN50XX ISA 64 */
1102#define MIPS_CN52XX 0x07 /* Cavium Octeon CN52XX ISA 64 */
1103#define MIPS_CN63XX 0x90 /* Cavium Octeon CN63XX ISA 64 */
1104#define MIPS_CN68XX 0x91 /* Cavium Octeon CN68XX ISA 64 */
1105#define MIPS_CN66XX 0x92 /* Cavium Octeon CN66XX ISA 64 */
1106#define MIPS_CN61XX 0x93 /* Cavium Octeon CN61XX ISA 64 */
1107#define MIPS_CNF71XX 0x94 /* Cavium Octeon CNF71XX ISA 64 */
1108#define MIPS_CN78XX 0x95 /* Cavium Octeon CN78XX ISA 64 */
1109#define MIPS_CN70XX 0x96 /* Cavium Octeon CN70XX ISA 64 */
1110#define MIPS_CN73XX 0x97 /* Cavium Octeon CN73XX ISA 64 */
1111#define MIPS_CNF75XX 0x98 /* Cavium Octeon CNF75XX ISA 64 */
1112
1113/*
1114 * CPU processor revision IDs for company ID == 7 (Microsoft)
1115 */
1116#define MIPS_eMIPS 0x04 /* MSR's eMIPS */
1117
1118/*
1119 * CPU processor revision IDs for company ID == e1 (Ingenic)
1120 */
1121#define MIPS_XBURST 0x02 /* Ingenic XBurst */
1122
1123/*
1124 * FPU processor revision ID
1125 */
1126#define MIPS_SOFT 0x00 /* Software emulation ISA I */
1127#define MIPS_R2360 0x01 /* MIPS R2360 FPC ISA I */
1128#define MIPS_R2010 0x02 /* MIPS R2010 FPC ISA I */
1129#define MIPS_R3010 0x03 /* MIPS R3010 FPC ISA I */
1130#define MIPS_R6010 0x04 /* MIPS R6010 FPC ISA II */
1131#define MIPS_R4010 0x05 /* MIPS R4010 FPC ISA II */
1132#define MIPS_R31LSI 0x06 /* LSI Logic derivate ISA I */
1133#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based FPU ISA I */
1134
1135#ifdef ENABLE_MIPS_TX3900
1136#include <mips/r3900regs.h>
1137#endif
1138#ifdef MIPS64_SB1
1139#include <mips/sb1regs.h>
1140#endif
1141#if defined(MIPS64_XLP) || defined(MIPS64_XLR) || defined(MIPS64_XLS)
1142#include <mips/rmi/rmixlreg.h>
1143#endif
1144
1145#ifdef MIPS3_LOONGSON2
1146/*
1147 * Loongson 2E/2F specific defines
1148 */
1149
1150/*
1151 * Address Window registers physical addresses
1152 *
1153 * The Loongson 2F processor has an AXI crossbar with four possible bus
1154 * masters, each one having four programmable address windows.
1155 *
1156 * Each window is defined with three 64-bit registers:
1157 * - a base address register, defining the address in the master address
1158 * space (base register).
1159 * - an address mask register, defining which address bits are valid in this
1160 * window. A given address matches a window if (addr & mask) == base.
1161 * - the location of the window base in the target, as well at the target
1162 * number itself (mmap register). The lower 20 bits of the address are
1163 * forced as zeroes regardless of their value in this register.
1164 * The translated address is thus (addr & ~mask) | (mmap & ~0xfffff).
1165 */
1166
1167#define LOONGSON_AWR_BASE_ADDRESS 0x3ff00000ULL
1168
1169#define LOONGSON_AWR_BASE(master, window) \
1170 (LOONGSON_AWR_BASE_ADDRESS + (window) * 0x08 + (master) * 0x60 + 0x00)
1171#define LOONGSON_AWR_SIZE(master, window) \
1172 (LOONGSON_AWR_BASE_ADDRESS + (window) * 0x08 + (master) * 0x60 + 0x20)
1173#define LOONGSON_AWR_MMAP(master, window) \
1174 (LOONGSON_AWR_BASE_ADDRESS + (window) * 0x08 + (master) * 0x60 + 0x40)
1175
1176/*
1177 * Bits in the diagnostic register
1178 */
1179
1180#define COP_0_DIAG_ITLB_CLEAR 0x04
1181#define COP_0_DIAG_BTB_CLEAR 0x02
1182#define COP_0_DIAG_RAS_DISABLE 0x01
1183
1184#endif /* MIPS3_LOONGSON2 */
1185
1186#endif /* _MIPS_CPUREGS_H_ */