1/* $NetBSD: mips3_pte.h,v 1.32 2023/09/09 18:49:21 andvar Exp $ */
2
3/*
4 * Copyright (c) 1988 University of Utah.
5 * Copyright (c) 1992, 1993
6 * The Regents of the University of California. All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer
10 * Science Department and Ralph Campbell.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * from: Utah Hdr: pte.h 1.11 89/09/03
37 *
38 * from: @(#)pte.h 8.1 (Berkeley) 6/10/93
39 */
40
41#ifndef _MIPS_MIPS3_PTE_H_
42#define _MIPS_MIPS3_PTE_H_
43
44/*
45 * R4000 hardware page table entry
46 */
47
48#ifndef _LOCORE
49#if 0
50struct mips3_pte {
51#if BYTE_ORDER == BIG_ENDIAN
52unsigned int pg_prot:2, /* SW: access control */
53 pg_pfnum:24, /* HW: core page frame number or 0 */
54 pg_attr:3, /* HW: cache attribute */
55 pg_m:1, /* HW: dirty bit */
56 pg_v:1, /* HW: valid bit */
57 pg_g:1; /* HW: ignore asid bit */
58#endif
59#if BYTE_ORDER == LITTLE_ENDIAN
60unsigned int pg_g:1, /* HW: ignore asid bit */
61 pg_v:1, /* HW: valid bit */
62 pg_m:1, /* HW: dirty bit */
63 pg_attr:3, /* HW: cache attribute */
64 pg_pfnum:24, /* HW: core page frame number or 0 */
65 pg_prot:2; /* SW: access control */
66#endif
67};
68#endif
69#endif /* _LOCORE */
70
71#define MIPS3_PG_WIRED 0x80000000 /* SW */
72#define MIPS3_PG_RO 0x40000000 /* SW */
73
74#if PGSHIFT == 14
75#define MIPS3_PG_SVPN (~0UL << 14) /* Software page no mask */
76#define MIPS3_PG_HVPN (~0UL << 15) /* Hardware page no mask */
77#define MIPS3_PG_ODDPG (MIPS3_PG_SVPN ^ MIPS3_PG_HVPN)
78#elif PGSHIFT == 13
79#ifdef MIPS3_4100
80#error 8KB page size is not supported on the MIPS3_4100
81#endif
82#define MIPS3_PG_SVPN (~0UL << 13) /* Software page no mask */
83#define MIPS3_PG_HVPN (~0UL << 13) /* Hardware page no mask */
84#define MIPS3_PG_NEXT (1 << (12 - MIPS3_DEFAULT_PG_SHIFT))
85#elif PGSHIFT == 12
86#define MIPS3_PG_SVPN (~0UL << 12) /* Software page no mask */
87#define MIPS3_PG_HVPN (~0UL << 13) /* Hardware page no mask */
88#define MIPS3_PG_ODDPG (MIPS3_PG_SVPN ^ MIPS3_PG_HVPN)
89#endif
90 /* Odd even pte entry */
91#define MIPS3_PG_ASID 0x000000ff /* Address space ID */
92#define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
93#define MIPS3_PG_V 0x00000002 /* Valid */
94#define MIPS3_PG_NV 0x00000000
95#define MIPS3_PG_D 0x00000004 /* Dirty */
96#define MIPS3_PG_ATTR 0x0000003f
97
98#define MIPS3_CCA_TO_PG(cca) ((cca) << 3)
99#define MIPS3_PG_TO_CCA(cca) (((cca) >> 3) & 7)
100
101#define MIPS3_XPHYS_UNCACHED MIPS_PHYS_TO_XKPHYS(2, 0)
102#define MIPS3_XPHYS_ACC MIPS_PHYS_TO_XKPHYS(mips_options.mips3_cca_devmem, 0)
103
104#define MIPS3_PG_UNCACHED MIPS3_CCA_TO_PG(2)
105#define MIPS3_PG_WT MIPS3_CCA_TO_PG(5)
106#define MIPS3_PG_ACC MIPS3_CCA_TO_PG(mips_options.mips3_cca_devmem)
107#ifdef HPCMIPS_L1CACHE_DISABLE /* MIPS3_L1CACHE_DISABLE */
108#define MIPS3_DEFAULT_XKPHYS_CACHED MIPS3_DEFAULT_XKPHYS_UNCACHED
109#define MIPS3_PG_CACHED MIPS3_PG_UNCACHED /* XXX: brain damaged!!! */
110#else /* HPCMIPS_L1CACHE_DISABLE */
111#define MIPS3_DEFAULT_XKPHYS_CACHED MIPS_PHYS_TO_XKPHYS(3, 0)
112#define MIPS3_PG_CACHED mips_options.mips3_pg_cached
113#define MIPS3_DEFAULT_PG_CACHED MIPS3_CCA_TO_PG(3)
114#endif /* ! HPCMIPS_L1CACHE_DISABLE */
115#define MIPS3_PG_CACHEMODE MIPS3_CCA_TO_PG(7)
116
117/* Write protected */
118#define MIPS3_PG_ROPAGE (MIPS3_PG_V | MIPS3_PG_RO | MIPS3_PG_CACHED)
119
120/* Not wr-prot not clean */
121#define MIPS3_PG_RWPAGE (MIPS3_PG_V | MIPS3_PG_D | MIPS3_PG_CACHED)
122
123/* Not wr-prot not clean not cached */
124#define MIPS3_PG_RWNCPAGE (MIPS3_PG_V | MIPS3_PG_D | MIPS3_PG_UNCACHED)
125
126/* Not wr-prot not clean not cached, accel */
127#define MIPS3_PG_RWAPAGE (MIPS3_PG_V | MIPS3_PG_D | MIPS3_PG_ACC)
128
129/* Not wr-prot but clean */
130#define MIPS3_PG_CWPAGE (MIPS3_PG_V | MIPS3_PG_CACHED)
131
132/* Not wr-prot but clean not cached*/
133#define MIPS3_PG_CWNCPAGE (MIPS3_PG_V | MIPS3_PG_UNCACHED)
134
135/* Not wr-prot but clean not cached, accel*/
136#define MIPS3_PG_CWAPAGE (MIPS3_PG_V | MIPS3_PG_ACC)
137
138#define MIPS3_PG_IOPAGE(cca) \
139 (MIPS3_PG_G | MIPS3_PG_V | MIPS3_PG_D | MIPS3_CCA_TO_PG(cca))
140#define MIPS3_PG_FRAME 0x3fffffc0
141
142#define MIPS3_DEFAULT_PG_SHIFT 6
143#define MIPS3_4100_PG_SHIFT 4
144
145/* NEC Vr4100 CPUs have different PFN layout to support 1kbytes/page */
146#if defined(MIPS3_4100)
147#define MIPS3_PG_SHIFT mips_options.mips3_pg_shift
148#else
149#define MIPS3_PG_SHIFT MIPS3_DEFAULT_PG_SHIFT
150#endif
151
152/* pte accessor macros */
153
154#define mips3_pfn_is_ext(x) ((x) & 0x3c000000)
155#define mips3_paddr_to_tlbpfn(x) \
156 (((paddr_t)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
157#define mips3_tlbpfn_to_paddr(x) \
158 ((paddr_t)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
159#define mips3_vad_to_vpn(x) ((vaddr_t)(x) & MIPS3_PG_SVPN)
160#define mips3_vpn_to_vad(x) ((x) & MIPS3_PG_SVPN)
161
162#define MIPS3_PTE_TO_PADDR(pte) (mips3_tlbpfn_to_paddr(pte))
163#define MIPS3_PAGE_IS_RDONLY(pte,va) \
164 (pmap_is_page_ro_p(pmap_kernel(), mips_trunc_page(va), (pte)))
165
166
167#define MIPS3_PG_SIZE_4K 0x00000000
168#define MIPS3_PG_SIZE_16K 0x00006000
169#define MIPS3_PG_SIZE_64K 0x0001e000
170#define MIPS3_PG_SIZE_256K 0x0007e000
171#define MIPS3_PG_SIZE_1M 0x001fe000
172#define MIPS3_PG_SIZE_4M 0x007fe000
173#define MIPS3_PG_SIZE_16M 0x01ffe000
174#define MIPS3_PG_SIZE_64M 0x07ffe000
175#define MIPS3_PG_SIZE_256M 0x1fffe000
176
177#ifdef _KERNEL
178#define MIPS3_PG_SIZE_MASK_TO_SIZE(pg_mask) \
179 ((((pg_mask) | 0x00001fff) + 1) / 2)
180
181#define MIPS3_PG_SIZE_TO_MASK(pg_size) \
182 ((((pg_size) << (((pg_size) & 0x2aaaa) == 0)) - 1) & ~0x00001fff)
183
184CTASSERT(MIPS3_PG_SIZE_TO_MASK(4096) == MIPS3_PG_SIZE_4K);
185CTASSERT(MIPS3_PG_SIZE_TO_MASK(8192) == MIPS3_PG_SIZE_4K);
186#endif
187
188/* NEC Vr41xx uses different pagemask values. */
189#define MIPS4100_PG_SIZE_1K 0x00000000
190#define MIPS4100_PG_SIZE_4K 0x00001800
191#define MIPS4100_PG_SIZE_16K 0x00007800
192#define MIPS4100_PG_SIZE_64K 0x0001f800
193#define MIPS4100_PG_SIZE_256K 0x0007f800
194
195#define MIPS4100_PG_SIZE_MASK_TO_SIZE(pg_mask) \
196 ((((pg_mask) | 0x000007ff) + 1) / 2)
197
198#define MIPS4100_PG_SIZE_TO_MASK(pg_size) \
199 ((((pg_size) * 2) - 1) & ~0x000007ff)
200
201#endif /* !_MIPS_MIPS3_PTE_H_ */