1/* $NetBSD: mips_opcode.h,v 1.26 2021/04/05 07:28:19 simonb Exp $ */
2
3/*-
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * @(#)mips_opcode.h 8.1 (Berkeley) 6/10/93
35 */
36
37#ifndef _MIPS_MIPS_OPCODE_H_
38#define _MIPS_MIPS_OPCODE_H_
39
40/*
41 * Define the instruction formats and opcode values for the
42 * MIPS instruction set.
43 */
44
45/*
46 * Define the instruction formats.
47 */
48typedef union {
49 unsigned word;
50
51#if BYTE_ORDER == LITTLE_ENDIAN
52 struct {
53 unsigned imm: 16;
54 unsigned rt: 5;
55 unsigned rs: 5;
56 unsigned op: 6;
57 } IType;
58
59 struct {
60 unsigned target: 26;
61 unsigned op: 6;
62 } JType;
63
64 struct {
65 unsigned func: 6;
66 unsigned shamt: 5;
67 unsigned rd: 5;
68 unsigned rt: 5;
69 unsigned rs: 5;
70 unsigned op: 6;
71 } RType;
72
73 struct {
74 unsigned func: 6;
75 unsigned fd: 5;
76 unsigned fs: 5;
77 unsigned ft: 5;
78 unsigned fmt: 4;
79 unsigned : 1; /* always '1' */
80 unsigned op: 6; /* always '0x11' */
81 } FRType;
82
83 struct {
84 unsigned func: 6;
85 unsigned zero: 1; /* always '0' */
86 unsigned offset: 9;
87 unsigned rt: 5;
88 unsigned rs: 5;
89 unsigned op: 6;
90 } S3OType; /* has "special3 offset" type */
91
92#endif
93#if BYTE_ORDER == BIG_ENDIAN
94 struct {
95 unsigned op: 6;
96 unsigned rs: 5;
97 unsigned rt: 5;
98 unsigned imm: 16;
99 } IType;
100
101 struct {
102 unsigned op: 6;
103 unsigned target: 26;
104 } JType;
105
106 struct {
107 unsigned op: 6;
108 unsigned rs: 5;
109 unsigned rt: 5;
110 unsigned rd: 5;
111 unsigned shamt: 5;
112 unsigned func: 6;
113 } RType;
114
115 struct {
116 unsigned op: 6; /* always '0x11' */
117 unsigned : 1; /* always '1' */
118 unsigned fmt: 4;
119 unsigned ft: 5;
120 unsigned fs: 5;
121 unsigned fd: 5;
122 unsigned func: 6;
123 } FRType;
124
125 struct {
126 unsigned op: 6;
127 unsigned rs: 5;
128 unsigned rt: 5;
129 unsigned offset: 9;
130 unsigned zero: 1; /* always '0' */
131 unsigned func: 6;
132 } S3OType; /* has "special3 offset" type */
133
134#endif
135} InstFmt;
136
137/*
138 * Values for the 'op' field.
139 */
140#define OP_SPECIAL 000
141#define OP_REGIMM 001
142#define OP_J 002
143#define OP_JAL 003
144#define OP_BEQ 004
145#define OP_BNE 005
146#define OP_BLEZ 006
147#define OP_BGTZ 007
148
149#define OP_ADDI 010
150#define OP_ADDIU 011
151#define OP_SLTI 012
152#define OP_SLTIU 013
153#define OP_ANDI 014
154#define OP_ORI 015
155#define OP_XORI 016
156#define OP_LUI 017
157
158#define OP_COP0 020
159#define OP_COP1 021
160#define OP_COP2 022
161#define OP_COP3 023
162#define OP_BEQL 024 /* MIPS-II, for r4000 port */
163#define OP_BNEL 025 /* MIPS-II, for r4000 port */
164#define OP_BLEZL 026 /* MIPS-II, for r4000 port */
165#define OP_BGTZL 027 /* MIPS-II, for r4000 port */
166
167#define OP_DADDI 030 /* MIPS-II, for r4000 port */
168#define OP_DADDIU 031 /* MIPS-II, for r4000 port */
169#define OP_LDL 032 /* MIPS-II, for r4000 port */
170#define OP_LDR 033 /* MIPS-II, for r4000 port */
171
172#define OP_SPECIAL2 034 /* QED and MIPS32/MIPS64 opcodes */
173#define OP_JALX 035
174#define OP_MDMX 036
175#define OP_SPECIAL3 037
176
177#define OP_LB 040
178#define OP_LH 041
179#define OP_LWL 042
180#define OP_LW 043
181#define OP_LBU 044
182#define OP_LHU 045
183#define OP_LWR 046
184#define OP_LHU 045
185#define OP_LWR 046
186#define OP_LWU 047 /* MIPS-II, for r4000 port */
187
188#define OP_SB 050
189#define OP_SH 051
190#define OP_SWL 052
191#define OP_SW 053
192#define OP_SDL 054 /* MIPS-II, for r4000 port */
193#define OP_SDR 055 /* MIPS-II, for r4000 port */
194#define OP_SWR 056
195#define OP_CACHE 057 /* MIPS-II, for r4000 port */
196
197#define OP_LL 060
198#define OP_LWC0 OP_LL /* backwards source compatibility */
199#define OP_LWC1 061
200#define OP_LWC2 062
201#define OP_PREF 063
202#define OP_LLD 064 /* MIPS-II, for r4000 port */
203#define OP_LDC1 065
204#define OP_LDC2 066
205#define OP_LD 067 /* MIPS-II, for r4000 port */
206#define OP_CVM_BBIT0 OP_LWC2
207#define OP_CVM_BBIT032 OP_LDC2
208
209#define OP_SC 070
210#define OP_SWC0 OP_SC /* backwards source compatibility */
211#define OP_SWC1 071
212#define OP_SWC2 072
213#define OP_RSVD073 073
214#define OP_SCD 074 /* MIPS-II, for r4000 port */
215#define OP_SDC1 075
216#define OP_SDC2 076
217#define OP_SD 077 /* MIPS-II, for r4000 port */
218#define OP_CVM_BBIT1 OP_SWC2
219#define OP_CVM_BBIT132 OP_SDC2
220
221/*
222 * Values for the 'func' field when 'op' == OP_SPECIAL.
223 */
224#define OP_SLL 000
225#define OP_SRL 002
226#define OP_SRA 003
227#define OP_SLLV 004
228#define OP_SRLV 006
229#define OP_SRAV 007
230
231#define OP_JR 010
232#define OP_JALR 011
233#define OP_SYSCALL 014
234#define OP_BREAK 015
235#define OP_SYNC 017 /* MIPS-II, for r4000 port */
236
237#define SYNC_CVM_IODBDMA 0x02
238#define SYNC_WMB 0x04
239#define SYNC_CVM_W SYNC_WMB
240#define SYNC_CVM_WS 0x05
241#define SYNC_CVM_S 0x06
242#define SYNC_MB 0x10
243#define SYNC_ACQUIRE 0x11
244#define SYNC_RELEASE 0x12
245#define SYNC_RMB 0x13
246
247#define OP_MFHI 020
248#define OP_MTHI 021
249#define OP_MFLO 022
250#define OP_MTLO 023
251#define OP_DSLLV 024 /* MIPS-II, for r4000 port */
252#define OP_DSRLV 026 /* MIPS-II, for r4000 port */
253#define OP_DSRAV 027 /* MIPS-II, for r4000 port */
254
255#define OP_MULT 030
256#define OP_MULTU 031
257#define OP_DIV 032
258#define OP_DIVU 033
259#define OP_DMULT 034 /* MIPS-II, for r4000 port */
260#define OP_DMULTU 035 /* MIPS-II, for r4000 port */
261#define OP_DDIV 036 /* MIPS-II, for r4000 port */
262#define OP_DDIVU 037 /* MIPS-II, for r4000 port */
263
264#define OP_ADD 040
265#define OP_ADDU 041
266#define OP_SUB 042
267#define OP_SUBU 043
268#define OP_AND 044
269#define OP_OR 045
270#define OP_XOR 046
271#define OP_NOR 047
272
273#define OP_SLT 052
274#define OP_SLTU 053
275#define OP_DADD 054 /* MIPS-II, for r4000 port */
276#define OP_DADDU 055 /* MIPS-II, for r4000 port */
277#define OP_DSUB 056 /* MIPS-II, for r4000 port */
278#define OP_DSUBU 057 /* MIPS-II, for r4000 port */
279
280#define OP_TGE 060 /* MIPS-II, for r4000 port */
281#define OP_TGEU 061 /* MIPS-II, for r4000 port */
282#define OP_TLT 062 /* MIPS-II, for r4000 port */
283#define OP_TLTU 063 /* MIPS-II, for r4000 port */
284#define OP_TEQ 064 /* MIPS-II, for r4000 port */
285#define OP_TNE 066 /* MIPS-II, for r4000 port */
286
287#define OP_DSLL 070 /* MIPS-II, for r4000 port */
288#define OP_DSRL 072 /* MIPS-II, for r4000 port */
289#define OP_DSRA 073 /* MIPS-II, for r4000 port */
290#define OP_DSLL32 074 /* MIPS-II, for r4000 port */
291#define OP_DSRL32 076 /* MIPS-II, for r4000 port */
292#define OP_DSRA32 077 /* MIPS-II, for r4000 port */
293
294/*
295 * Subvalues for SLL where the source and destination registers
296 * are both zero.
297 */
298#define OP_SLL_NOP 0
299#define OP_SLL_SSNOP 1
300#define OP_SLL_EHB 3
301#define OP_SLL_PAUSE 5
302
303/*
304 * Values for the 'func' field when 'op' == OP_SPECIAL2.
305 */
306#define OP_MADD 000 /* QED, MIPS32/64 */
307#define OP_MADDU 001 /* QED, MIPS32/64 */
308#define OP_MUL 002 /* QED, MIPS32/64 */
309#define OP_CVM_DMUL 003 /* OCTEON */
310#define OP_MSUB 004 /* MIPS32/64 */
311#define OP_MSUBU 005 /* MIPS32/64 */
312#define OP_CVM_SAA 030 /* OCTEON */
313#define OP_CVM_SAAD 031 /* OCTEON */
314#define OP_CLZ 040 /* MIPS32/64 */
315#define OP_CLO 041 /* MIPS32/64 */
316#define OP_DCLZ 044 /* MIPS32/64 */
317#define OP_DCLO 045 /* MIPS32/64 */
318#define OP_CVM_BADDU 050 /* OCTEON */
319#define OP_CVM_SEQ 052 /* OCTEON */
320#define OP_CVM_SNE 053 /* OCTEON */
321#define OP_CVM_SEQI 056 /* OCTEON */
322#define OP_CVM_SNEI 057 /* OCTEON */
323#define OP_CVM_POP 054 /* OCTEON */
324#define OP_CVM_DPOP 055 /* OCTEON */
325#define OP_CVM_CINS 062 /* OCTEON */
326#define OP_CVM_CINS32 063 /* OCTEON */
327#define OP_CVM_EXTS 072 /* OCTEON */
328#define OP_CVM_EXTS32 073 /* OCTEON */
329#define OP_SDBBP 077 /* MIPS32/MIPS64 */
330
331/*
332 * Values for the 'func' field when 'op' == OP_SPECIAL3.
333 */
334#define OP_EXT 000 /* MIPS32/64 r2 */
335#define OP_DEXTM 001 /* MIPS32/64 r2 */
336#define OP_DEXTU 002 /* MIPS32/64 r2 */
337#define OP_DEXT 003 /* MIPS32/64 r2 */
338#define OP_INS 004 /* MIPS32/64 r2 */
339#define OP_DINSM 005 /* MIPS32/64 r2 */
340#define OP_DINSU 006 /* MIPS32/64 r2 */
341#define OP_DINS 007 /* MIPS32/64 r2 */
342#define OP_LX 012 /* DSP */
343#define OP_LWLE 031 /* EVA */
344#define OP_LWRE 032 /* EVA */
345#define OP_CACHEE 033 /* EVA */
346#define OP_SBE 034 /* EVA */
347#define OP_SHE 035 /* EVA */
348#define OP_SCE 036 /* EVA */
349#define OP_SWE 037 /* EVA */
350#define OP_BSHFL 040 /* MIPS32/64 r2 */
351#define OP_SWLE 041 /* EVA */
352#define OP_SWRE 042 /* EVA */
353#define OP_PREFE 043 /* EVA */
354#define OP_DBSHFL 044 /* MIPS32/64 r2 */
355#define OP_CACHE_R6 045 /* MIPS32/64 r6 */
356#define OP_LBUE 050 /* EVA */
357#define OP_LHUE 051 /* EVA */
358#define OP_LBE 054 /* EVA */
359#define OP_LHE 055 /* EVA */
360#define OP_LLE 056 /* EVA */
361#define OP_LWE 057 /* EVA */
362#define OP_RDHWR 073 /* MIPS32/64 r2 */
363
364#define OP_BSHFL_SBH 002 /* swap bytes within halfwords */
365#define OP_BSHFL_SHD 005 /* swap halfworks within double */
366#define OP_BSHFL_SEB 020 /* sign extend byte */
367#define OP_BSHFL_SEH 030 /* sign extend halfword */
368
369#define OP_LX_LWX 0 /* lwx */
370#define OP_LX_LHX 4 /* lhx */
371#define OP_LX_LBUX 6 /* lbux */
372#define OP_LX_LDX 8 /* ldx */
373
374/*
375 * Values for the 'func' field when 'op' == OP_REGIMM.
376 */
377#define OP_BLTZ 000
378#define OP_BGEZ 001
379#define OP_BLTZL 002 /* MIPS-II, for r4000 port */
380#define OP_BGEZL 003 /* MIPS-II, for r4000 port */
381
382#define OP_TGEI 010 /* MIPS-II, for r4000 port */
383#define OP_TGEIU 011 /* MIPS-II, for r4000 port */
384#define OP_TLTI 012 /* MIPS-II, for r4000 port */
385#define OP_TLTIU 013 /* MIPS-II, for r4000 port */
386#define OP_TEQI 014 /* MIPS-II, for r4000 port */
387#define OP_TNEI 016 /* MIPS-II, for r4000 port */
388
389#define OP_BLTZAL 020 /* MIPS-II, for r4000 port */
390#define OP_BGEZAL 021
391#define OP_BLTZALL 022
392#define OP_BGEZALL 023
393
394/*
395 * Values for the 'rs' field when 'op' == OP_COPz.
396 */
397#define OP_MF 000
398#define OP_DMF 001 /* MIPS-II, for r4000 port */
399#define OP_CF 002
400#define OP_MFH 003
401#define OP_MT 004
402#define OP_DMT 005 /* MIPS-II, for r4000 port */
403#define OP_CT 006
404#define OP_MTH 007
405#define OP_BCx 010
406#define OP_MFM 013 /* MIPS32/64 r2 */
407#define OP_BCy 014
408
409/*
410 * Values for the 'rt' field when 'op' == OP_COPz.
411 */
412#define COPz_BC_TF_MASK 0x01
413#define COPz_BC_TRUE 0x01
414#define COPz_BC_FALSE 0x00
415#define COPz_BCL_TF_MASK 0x02 /* MIPS-II, for r4000 port */
416#define COPz_BCL_TRUE 0x02 /* MIPS-II, for r4000 port */
417#define COPz_BCL_FALSE 0x00 /* MIPS-II, for r4000 port */
418
419#define INSN_LUI_P(insn) (((insn) >> 26) == OP_LUI)
420#define INSN_LW_P(insn) (((insn) >> 26) == OP_LW)
421#define INSN_SW_P(insn) (((insn) >> 26) == OP_SW)
422#define INSN_LD_P(insn) (((insn) >> 26) == OP_LD)
423#define INSN_SD_P(insn) (((insn) >> 26) == OP_SD)
424
425#define INSN_LOAD_P(insn) (INSN_LD_P(insn) || INSN_LW_P(insn))
426#define INSN_STORE_P(insn) (INSN_SD_P(insn) || INSN_SW_P(insn))
427
428#endif /* _MIPS_MIPS_OPCODE_H_ */