1/* $NetBSD: mips_param.h,v 1.56 2025/05/03 02:00:57 riastradh Exp $ */
2
3/*-
4 * Copyright (c) 2013 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
17 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 * POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef _MIPS_MIPS_PARAM_H_
30#define _MIPS_MIPS_PARAM_H_
31
32#ifdef _KERNEL_OPT
33#include "opt_cputype.h"
34#include "opt_param.h"
35#endif
36
37/*
38 * No reason this can't be common
39 */
40#if defined(__MIPSEB__)
41# define _MACHINE_SUFFIX eb
42# define MACHINE_SUFFIX "eb"
43#elif defined(__MIPSEL__)
44# define _MACHINE_SUFFIX el
45# define MACHINE_SUFFIX "el"
46#else
47# error neither __MIPSEL__ nor __MIPSEB__ are defined.
48#endif
49
50#define ___MACHINE32_OARCH mips##_MACHINE_SUFFIX
51#define __MACHINE32_OARCH "mips" MACHINE_SUFFIX
52#define ___MACHINE32_NARCH mips64##_MACHINE_SUFFIX
53#define __MACHINE32_NARCH "mips64" MACHINE_SUFFIX
54#define ___MACHINE64_NARCH mipsn64##_MACHINE_SUFFIX
55#define __MACHINE64_NARCH "mipsn64" MACHINE_SUFFIX
56
57#if defined(__mips_n32) || defined(__mips_n64)
58# if defined(__mips_n32)
59# define _MACHINE_ARCH ___MACHINE32_NARCH
60# define MACHINE_ARCH __MACHINE32_NARCH
61# else /* __mips_n64 */
62# define _MACHINE_ARCH ___MACHINE64_NARCH
63# define MACHINE_ARCH __MACHINE64_NARCH
64# define _MACHINE32_NARCH ___MACHINE32_NARCH
65# define MACHINE32_NARCH __MACHINE32_NARCH
66# endif
67# define _MACHINE32_OARCH ___MACHINE32_OARCH
68# define MACHINE32_OARCH __MACHINE32_OARCH
69#else /* o32 */
70# define _MACHINE_ARCH ___MACHINE32_OARCH
71# define MACHINE_ARCH __MACHINE32_OARCH
72#endif
73
74/*
75 * Userland code should be using uname/sysctl to get MACHINE so simply
76 * export a generic MACHINE of "mips"
77 */
78#ifndef _KERNEL
79#undef MACHINE
80#define MACHINE "mips"
81#endif
82
83#if defined(__mips_n64) || defined(__mips_n32)
84#define STACK_ALIGNBYTES (16 - 1)
85#else
86#define STACK_ALIGNBYTES (8 - 1)
87#endif
88
89#define STACK_ALIGNBYTES_O32 (8 - 1)
90
91#define ALIGNBYTES32 (sizeof(double) - 1)
92#define ALIGN32(p) (((uintptr_t)(p) + ALIGNBYTES32) &~ALIGNBYTES32)
93
94/*
95 * On mips, UPAGES is fixed by sys/arch/mips/mips/locore code
96 * to be the number of per-process-wired kernel-stack pages/PTES.
97 */
98
99#define SSIZE 1 /* initial stack size/NBPG */
100#define SINCR 1 /* increment of stack/NBPG */
101
102#if (ENABLE_MIPS_16KB_PAGE + ENABLE_MIPS_8KB_PAGE + ENABLE_MIPS_4KB_PAGE) > 1
103#error only one of ENABLE_MIPS_{4,8,16}KB_PAGE can be defined.
104#endif
105
106#ifndef MSGBUFSIZE
107#define MSGBUFSIZE NBPG /* default message buffer size */
108#endif
109
110/*
111 * Most MIPS have a cache line size of 32 bytes, but Cavium chips
112 * have a line size 128 bytes and we need to cover the larger size.
113 */
114#define COHERENCY_UNIT 128
115#define CACHE_LINE_SIZE 128
116
117#ifdef ENABLE_MIPS_16KB_PAGE
118#define PGSHIFT 14 /* LOG2(NBPG) */
119#elif defined(ENABLE_MIPS_8KB_PAGE) \
120 || (!defined(ENABLE_MIPS_4KB_PAGE) && __mips >= 3)
121#define PGSHIFT 13 /* LOG2(NBPG) */
122#else
123#define PGSHIFT 12 /* LOG2(NBPG) */
124#endif
125#define NBPG (1 << PGSHIFT) /* bytes/page */
126#define PGOFSET (NBPG - 1) /* byte offset into page */
127#define PTPSHIFT 2
128#define PTPLENGTH (PGSHIFT - PTPSHIFT)
129#define NPTEPG (1 << PTPLENGTH)
130
131#define SEGSHIFT (PGSHIFT + PTPLENGTH) /* LOG2(NBSEG) */
132#define NBSEG (1 << SEGSHIFT) /* bytes/segment */
133#define SEGOFSET (NBSEG - 1) /* byte offset into segment */
134
135#ifdef _LP64
136#define SEGLENGTH (PGSHIFT - 3)
137#define XSEGSHIFT (SEGSHIFT + SEGLENGTH) /* LOG2(NBXSEG) */
138#define NBXSEG (1UL << XSEGSHIFT) /* bytes/xsegment */
139#define XSEGOFSET (NBXSEG - 1) /* byte offset into xsegment */
140#define XSEGLENGTH (PGSHIFT - 3)
141#define NXSEGPG (1 << XSEGLENGTH)
142#else
143#define SEGLENGTH (31 - SEGSHIFT)
144#endif
145#define NSEGPG (1 << SEGLENGTH)
146
147#ifdef _LP64
148#define __MIN_USPACE 16384 /* LP64 needs a 16kB stack */
149#else
150/*
151 * Note for the non-LP64 case, cpu_switch_resume has the assumption
152 * that UPAGES == 2. For MIPS-I we wire USPACE in TLB #0 and #1.
153 * For MIPS3+ we wire USPACE in the TLB #0 pair.
154 */
155#define __MIN_USPACE 8192 /* otherwise use an 8kB stack */
156#endif
157#define USPACE MAX(__MIN_USPACE, PAGE_SIZE)
158#define UPAGES (USPACE / PAGE_SIZE) /* number of pages for u-area */
159#define USPACE_ALIGN USPACE /* make sure it starts on a even VA */
160#define UPAGES_MAX 8 /* a (constant) max for userland use */
161
162/*
163 * Minimum and maximum sizes of the kernel malloc arena in PAGE_SIZE-sized
164 * logical pages.
165 */
166#define NKMEMPAGES_MIN_DEFAULT ((8 * 1024 * 1024) >> PAGE_SHIFT)
167#define NKMEMPAGES_MAX_DEFAULT ((128 * 1024 * 1024) >> PAGE_SHIFT)
168
169/*
170 * Mach derived conversion macros
171 */
172#define mips_round_page(x) ((((uintptr_t)(x)) + NBPG - 1) & ~(NBPG-1))
173#define mips_trunc_page(x) ((uintptr_t)(x) & ~(NBPG-1))
174#define mips_btop(x) ((paddr_t)(x) >> PGSHIFT)
175#define mips_ptob(x) ((paddr_t)(x) << PGSHIFT)
176
177#ifdef __MIPSEL__
178#define MID_MACHINE MID_PMAX /* MID_PMAX (little-endian) */
179#endif
180#ifdef __MIPSEB__
181#define MID_MACHINE MID_MIPS /* MID_MIPS (big-endian) */
182#endif
183
184/*
185 * Constants related to network buffer management.
186 * MCLBYTES must be no larger than NBPG (the software page size), and,
187 * on machines that exchange pages of input or output buffers with mbuf
188 * clusters (MAPPED_MBUFS), MCLBYTES must also be an integral multiple
189 * of the hardware page size.
190 */
191#ifndef MSIZE
192#ifdef _LP64
193#define MSIZE 512 /* size of an mbuf */
194#else
195#define MSIZE 256 /* size of an mbuf */
196#endif
197
198#ifndef MCLSHIFT
199# define MCLSHIFT 11 /* convert bytes to m_buf clusters */
200#endif /* MCLSHIFT */
201
202#define MCLBYTES (1 << MCLSHIFT) /* size of a m_buf cluster */
203
204#endif
205
206#endif /* _MIPS_MIPS_PARAM_H_ */