| 1 | /*	$NetBSD: elf_support.h,v 1.1 2018/03/29 13:23:40 joerg Exp $	*/ |
| 2 | |
| 3 | /*- |
| 4 | * Copyright (c) 2000 Eduardo Horvath. |
| 5 | * Copyright (c) 2018 The NetBSD Foundation, Inc. |
| 6 | * All rights reserved. |
| 7 | * |
| 8 | * Redistribution and use in source and binary forms, with or without |
| 9 | * modification, are permitted provided that the following conditions |
| 10 | * are met: |
| 11 | * 1. Redistributions of source code must retain the above copyright |
| 12 | * notice, this list of conditions and the following disclaimer. |
| 13 | * 2. Redistributions in binary form must reproduce the above copyright |
| 14 | * notice, this list of conditions and the following disclaimer in the |
| 15 | * documentation and/or other materials provided with the distribution. |
| 16 | * |
| 17 | * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS |
| 18 | * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED |
| 19 | * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR |
| 20 | * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS |
| 21 | * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 22 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 23 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 24 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 25 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 26 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 27 | * POSSIBILITY OF SUCH DAMAGE. |
| 28 | */ |
| 29 | #ifndef _SPARC64_ELF_SUPPORT_H |
| 30 | #define _SPARC64_ELF_SUPPORT_H |
| 31 | |
| 32 | #ifdef __arch64__ |
| 33 | /* |
| 34 | * Create a jump to the location `target` starting at `where`. |
| 35 | * This requires up to 6 instructions. |
| 36 | * The first instruction is written last as it replaces a branch |
| 37 | * in the PLT during lazy binding. |
| 38 | * The resulting code can trash %g1 and %g5. |
| 39 | */ |
| 40 | static inline void |
| 41 | sparc_write_branch(void *where_, void *target) |
| 42 | { |
| 43 | 	const unsigned int BAA = 0x30800000U; /* ba,a (offset / 4) */ |
| 44 | 	const unsigned int SETHI = 0x03000000U; /* sethi %hi(0), %g1 */ |
| 45 | 	const unsigned int JMP = 0x81c06000U; /* jmpl %g1+%lo(0), %g0 */ |
| 46 | 	const unsigned int OR = 0x82106000U; /* or %g1, 0, %g1 */ |
| 47 | 	const unsigned int XOR = 0x82186000U; /* xor %g1, 0, %g1 */ |
| 48 | 	const unsigned int MOV71 = 0x8213e000U; /* or %o7, 0, %g1 */ |
| 49 | 	const unsigned int MOV17 = 0x9e106000U; /* or %g1, 0, %o7 */ |
| 50 | 	const unsigned int CALL = 0x40000000U; /* call 0 */ |
| 51 | 	const unsigned int SLLX = 0x83287000U; /* sllx %g1, 0, %g1 */ |
| 52 | 	const unsigned int NEG = 0x82200001U; /* neg %g1 */ |
| 53 | 	const unsigned int SETHIG5 = 0x0b000000U; /* sethi %hi(0), %g5 */ |
| 54 | 	const unsigned int ORG5 = 0x82104005U; /* or %g1, %g5, %g1 */ |
| 55 | |
| 56 | 	unsigned int *where = (unsigned int *)where_; |
| 57 | 	unsigned long value = (unsigned long)target; |
| 58 | 	unsigned long offset = value - (unsigned long)where; |
| 59 | |
| 60 | #define	HIVAL(v, s)	(((v) >> (s)) & 0x003fffffU) |
| 61 | #define	LOVAL(v, s)	(((v) >> (s)) & 0x000003ffU) |
| 62 | 	if (offset + 0x800000 <= 0x7ffffc) { |
| 63 | 		/* Displacement is within 8MB, use a direct branch. */ |
| 64 | 		where[0] = BAA | ((offset >> 2) & 0x3fffff); |
| 65 | 		__asm volatile("iflush %0+0" : : "r" (where)); |
| 66 | 		return; |
| 67 | 	} |
| 68 | |
| 69 | 	if (value <= 0xffffffffUL) { |
| 70 | 		/* |
| 71 | 		 * The absolute address is a 32bit value. |
| 72 | 		 * This can be encoded as: |
| 73 | 		 *	sethi	%hi(value), %g1 |
| 74 | 		 *	jmp	%g1+%lo(value) |
| 75 | 		 */ |
| 76 | 		where[1] = JMP | LOVAL(value, 0); |
| 77 | 		__asm volatile("iflush %0+4" : : "r" (where)); |
| 78 | 		where[0] = SETHI | HIVAL(value, 10); |
| 79 | 		__asm volatile("iflush %0+0" : : "r" (where)); |
| 80 | 		return; |
| 81 | 	} |
| 82 | |
| 83 | 	if (value >= 0xffffffff00000000UL) { |
| 84 | 		/* |
| 85 | 		 * The top 32bit address range can be encoded as: |
| 86 | 		 *	sethi	%hix(addr), %g1 |
| 87 | 		 *	xor	%g1, %lox(addr), %g1 |
| 88 | 		 *	jmp	%g1 |
| 89 | 		 */ |
| 90 | 		where[2] = JMP; |
| 91 | 		where[1] = XOR | (value & 0x00003ff) | 0x1c00; |
| 92 | 		__asm volatile("iflush %0+4" : : "r" (where)); |
| 93 | 		__asm volatile("iflush %0+8" : : "r" (where)); |
| 94 | 		where[0] = SETHI | HIVAL(~value, 10); |
| 95 | 		__asm volatile("iflush %0+0" : : "r" (where)); |
| 96 | 		return; |
| 97 | 	} |
| 98 | |
| 99 | 	if ((offset + 4) + 0x80000000UL <= 0x100000000UL) { |
| 100 | 		/* |
| 101 | 		 * Displacement of the second instruction is within |
| 102 | 		 * +-2GB. This can use a direct call instruction: |
| 103 | 		 *	mov	%o7, %g1 |
| 104 | 		 *	call	(value - .) |
| 105 | 		 *	 mov	%g1, %o7 |
| 106 | 		 */ |
| 107 | 		where[1] = CALL | ((-(offset + 4)>> 2) & 0x3fffffffU); |
| 108 | 		where[2] = MOV17; |
| 109 | 		__asm volatile("iflush %0+4" : : "r" (where)); |
| 110 | 		__asm volatile("iflush %0+8" : : "r" (where)); |
| 111 | 		where[0] = MOV71; |
| 112 | 		__asm volatile("iflush %0+0" : : "r" (where)); |
| 113 | 		return; |
| 114 | 	} |
| 115 | |
| 116 | 	if (value < 0x100000000000UL) { |
| 117 | 		/* |
| 118 | 		 * The absolute address is a 44bit value. |
| 119 | 		 * This can be encoded as: |
| 120 | 		 *	sethi	%h44(addr), %g1 |
| 121 | 		 *	or	%g1, %m44(addr), %g1 |
| 122 | 		 *	sllx	%g1, 12, %g1 |
| 123 | 		 *	jmp	%g1+%l44(addr) |
| 124 | 		 */ |
| 125 | 		where[1] = OR | (((value) >> 12) & 0x00001fff); |
| 126 | 		where[2] = SLLX | 12; |
| 127 | 		where[3] = JMP | LOVAL(value, 0); |
| 128 | 		__asm volatile("iflush %0+4" : : "r" (where)); |
| 129 | 		__asm volatile("iflush %0+8" : : "r" (where)); |
| 130 | 		__asm volatile("iflush %0+12" : : "r" (where)); |
| 131 | 		where[0] = SETHI | HIVAL(value, 22); |
| 132 | 		__asm volatile("iflush %0+0" : : "r" (where)); |
| 133 | 		return; |
| 134 | 	} |
| 135 | |
| 136 | 	if (value > 0xfffff00000000000UL) { |
| 137 | 		/* |
| 138 | 		 * The top 44bit address range can be encoded as: |
| 139 | 		 *	sethi	%hi((-addr)>>12), %g1 |
| 140 | 		 *	or	%g1, %lo((-addr)>>12), %g1 |
| 141 | 		 *	neg	%g1 |
| 142 | 		 *	sllx	%g1, 12, %g1 |
| 143 | 		 *	jmp	%g1+(addr&0x0fff) |
| 144 | 		 */ |
| 145 | 		unsigned long neg = (-value)>>12; |
| 146 | 		where[1] = OR | (LOVAL(neg, 0)+1); |
| 147 | 		where[2] = NEG; |
| 148 | 		where[3] = SLLX | 12; |
| 149 | 		where[4] = JMP | (value & 0x0fff); |
| 150 | 		__asm volatile("iflush %0+4" : : "r" (where)); |
| 151 | 		__asm volatile("iflush %0+8" : : "r" (where)); |
| 152 | 		__asm volatile("iflush %0+12" : : "r" (where)); |
| 153 | 		__asm volatile("iflush %0+16" : : "r" (where)); |
| 154 | 		where[0] = SETHI | HIVAL(neg, 10); |
| 155 | 		__asm volatile("iflush %0+0" : : "r" (where)); |
| 156 | 		return; |
| 157 | 	} |
| 158 | |
| 159 | 	/* |
| 160 | 	 * The general case of a 64bit address is encoded as: |
| 161 | 	 *	sethi	%hh(addr), %g1 |
| 162 | 	 *	sethi	%lm(addr), %g5 |
| 163 | 	 *	or	%g1, %hm(addr), %g1 |
| 164 | 	 *	sllx	%g1, 32, %g1 |
| 165 | 	 *	or	%g1, %g5, %g1 |
| 166 | 	 *	jmp	%g1+%lo(addr) |
| 167 | 	 */ |
| 168 | 	where[1] = SETHIG5 | HIVAL(value, 10); |
| 169 | 	where[2] = OR | LOVAL(value, 32); |
| 170 | 	where[3] = SLLX | 32; |
| 171 | 	where[4] = ORG5; |
| 172 | 	where[5] = JMP | LOVAL(value, 0); |
| 173 | 	__asm volatile("iflush %0+4" : : "r" (where)); |
| 174 | 	__asm volatile("iflush %0+8" : : "r" (where)); |
| 175 | 	__asm volatile("iflush %0+12" : : "r" (where)); |
| 176 | 	__asm volatile("iflush %0+16" : : "r" (where)); |
| 177 | 	__asm volatile("iflush %0+20" : : "r" (where)); |
| 178 | 	where[0] = SETHI | HIVAL(value, 42); |
| 179 | 	__asm volatile("iflush %0+0" : : "r" (where)); |
| 180 | #undef	HIVAL |
| 181 | #undef	LOVAL |
| 182 | } |
| 183 | #else |
| 184 | #include <sparc/elf_support.h> |
| 185 | #endif |
| 186 | #endif |