1/* $OpenBSD: cpu.h,v 1.151 2025/06/06 00:07:58 deraadt Exp $ */
2
3/*-
4 * Copyright (c) 1992, 1993
5 * The Regents of the University of California. All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * Ralph Campbell and Rick Macklem.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * Copyright (C) 1989 Digital Equipment Corporation.
35 * Permission to use, copy, modify, and distribute this software and
36 * its documentation for any purpose and without fee is hereby granted,
37 * provided that the above copyright notice appears in all copies.
38 * Digital Equipment Corporation makes no representations about the
39 * suitability of this software for any purpose. It is provided "as is"
40 * without express or implied warranty.
41 *
42 * from: @(#)cpu.h 8.4 (Berkeley) 1/4/94
43 */
44
45#ifndef _MIPS64_CPU_H_
46#define _MIPS64_CPU_H_
47
48#ifndef _LOCORE
49
50/*
51 * MIPS32-style segment definitions.
52 * They only cover the first 512MB of physical addresses.
53 */
54#define CKSEG0_BASE 0xffffffff80000000UL
55#define CKSEG1_BASE 0xffffffffa0000000UL
56#define CKSSEG_BASE 0xffffffffc0000000UL
57#define CKSEG3_BASE 0xffffffffe0000000UL
58#define CKSEG_SIZE 0x0000000020000000UL
59
60#define CKSEG0_TO_PHYS(x) ((u_long)(x) & (CKSEG_SIZE - 1))
61#define CKSEG1_TO_PHYS(x) ((u_long)(x) & (CKSEG_SIZE - 1))
62#define PHYS_TO_CKSEG0(x) ((u_long)(x) | CKSEG0_BASE)
63#define PHYS_TO_CKSEG1(x) ((u_long)(x) | CKSEG1_BASE)
64
65/*
66 * MIPS64-style segment definitions.
67 * These allow for 36 bits of addressable physical memory, thus 64GB.
68 */
69
70/*
71 * Cache Coherency Attributes.
72 */
73/* r8k only */
74#define CCA_NC_COPROCESSOR 0UL /* uncached, coprocessor ordered */
75/* common to r4, r5k, r8k and r1xk */
76#define CCA_NC 2UL /* uncached, write-around */
77#define CCA_NONCOHERENT 3UL /* cached, non-coherent, write-back */
78/* r8k, r1xk only */
79#define CCA_COHERENT_EXCL 4UL /* cached, coherent, exclusive */
80#define CCA_COHERENT_EXCLWRITE 5UL /* cached, coherent, exclusive write */
81/* r4k only */
82#define CCA_COHERENT_UPDWRITE 6UL /* cached, coherent, update on write */
83/* r1xk only */
84#define CCA_NC_ACCELERATED 7UL /* uncached accelerated */
85
86#ifdef TGT_COHERENT
87#define CCA_CACHED CCA_COHERENT_EXCLWRITE
88#else
89#define CCA_CACHED CCA_NONCOHERENT
90#endif
91
92#define XKSSSEG_BASE 0x4000000000000000UL
93#define XKPHYS_BASE 0x8000000000000000UL
94#define XKSSEG_BASE 0xc000000000000000UL
95
96#define XKPHYS_TO_PHYS(x) ((paddr_t)(x) & 0x0000000fffffffffUL)
97#define PHYS_TO_XKPHYS(x,c) ((paddr_t)(x) | XKPHYS_BASE | ((c) << 59))
98#define IS_XKPHYS(va) (((va) >> 62) == 2)
99#define XKPHYS_TO_CCA(x) (((x) >> 59) & 0x07)
100
101#endif /* _LOCORE */
102
103/*
104 * Exported definitions unique to mips cpu support.
105 */
106
107#if defined(_KERNEL) && !defined(_LOCORE)
108
109#include <sys/clockintr.h>
110#include <sys/device.h>
111#include <machine/intr.h>
112#include <sys/sched.h>
113#include <sys/srp.h>
114#include <uvm/uvm_percpu.h>
115
116struct cpu_hwinfo {
117 uint32_t c0prid;
118 uint32_t c1prid;
119 uint32_t clock; /* Hz */
120 uint32_t tlbsize;
121 uint type;
122 uint32_t l2size;
123};
124
125/*
126 * Cache memory configuration. One struct per cache.
127 */
128struct cache_info {
129 uint size; /* total cache size */
130 uint linesize; /* line size */
131 uint setsize; /* set size */
132 uint sets; /* number of sets */
133};
134
135struct cpu_info {
136 struct device *ci_dev; /* our device */
137 struct cpu_info *ci_self; /* pointer to this structure */
138 struct cpu_info *ci_next; /* next cpu */
139 struct proc *ci_curproc;
140 struct user *ci_curprocpaddr;
141 struct proc *ci_fpuproc; /* pointer to last proc to use FP */
142 uint32_t ci_delayconst;
143 struct cpu_hwinfo
144 ci_hw;
145
146#if defined(MULTIPROCESSOR)
147 struct srp_hazard ci_srp_hazards[SRP_HAZARD_NUM];
148#define __HAVE_UVM_PERCPU
149 struct uvm_pmr_cache ci_uvm;
150#endif
151
152 /* cache information and pending flush state */
153 uint ci_cacheconfiguration;
154 uint64_t ci_cachepending_l1i;
155 struct cache_info
156 ci_l1inst,
157 ci_l1data,
158 ci_l2,
159 ci_l3;
160
161 /* function pointers for the cache handling routines */
162 void (*ci_SyncCache)(struct cpu_info *);
163 void (*ci_InvalidateICache)(struct cpu_info *, vaddr_t,
164 size_t);
165 void (*ci_InvalidateICachePage)(struct cpu_info *, vaddr_t);
166 void (*ci_SyncICache)(struct cpu_info *);
167 void (*ci_SyncDCachePage)(struct cpu_info *, vaddr_t,
168 paddr_t);
169 void (*ci_HitSyncDCachePage)(struct cpu_info *, vaddr_t,
170 paddr_t);
171 void (*ci_HitSyncDCache)(struct cpu_info *, vaddr_t, size_t);
172 void (*ci_HitInvalidateDCache)(struct cpu_info *, vaddr_t,
173 size_t);
174 void (*ci_IOSyncDCache)(struct cpu_info *, vaddr_t, size_t,
175 int);
176
177 struct schedstate_percpu
178 ci_schedstate;
179 int ci_want_resched; /* need_resched() invoked */
180 cpuid_t ci_cpuid; /* our CPU ID */
181 uint32_t ci_randseed; /* per cpu random seed */
182 volatile int ci_ipl; /* software IPL */
183 uint32_t ci_softpending; /* pending soft interrupts */
184 int ci_clock_started;
185 volatile int ci_clock_deferred; /* clock interrupt postponed */
186 struct clockqueue
187 ci_queue;
188
189 struct pmap *ci_curpmap;
190 uint ci_idepth; /* interrupt depth */
191 volatile u_long ci_flags; /* flags; see below */
192 volatile int ci_ddb;
193#define CI_DDB_RUNNING 0
194#define CI_DDB_SHOULDSTOP 1
195#define CI_DDB_STOPPED 2
196#define CI_DDB_ENTERDDB 3
197#define CI_DDB_INDDB 4
198
199#ifdef DIAGNOSTIC
200 int ci_mutex_level;
201#endif
202#ifdef GPROF
203 struct gmonparam *ci_gmon;
204 struct clockintr ci_gmonclock;
205#endif
206 char ci_panicbuf[512];
207};
208
209#define CPUF_PRIMARY 0x01 /* CPU is primary CPU */
210#define CPUF_PRESENT 0x02 /* CPU is present */
211#define CPUF_RUNNING 0x04 /* CPU is running */
212
213extern struct cpu_info cpu_info_primary;
214extern struct cpu_info *cpu_info_list;
215#define CPU_INFO_ITERATOR int
216#define CPU_INFO_FOREACH(cii, ci) for (cii = 0, ci = cpu_info_list; \
217 ci != NULL; ci = ci->ci_next)
218
219#define CPU_INFO_UNIT(ci) ((ci)->ci_dev ? (ci)->ci_dev->dv_unit : 0)
220
221#define cpu_idle_enter() do { /* nothing */ } while (0)
222#define cpu_idle_leave() do { /* nothing */ } while (0)
223extern void (*cpu_idle_cycle_func)(void);
224#define cpu_idle_cycle() (*cpu_idle_cycle_func)()
225
226#ifdef MULTIPROCESSOR
227#define getcurcpu() hw_getcurcpu()
228#define setcurcpu(ci) hw_setcurcpu(ci)
229extern struct cpu_info *get_cpu_info(int);
230#define curcpu() getcurcpu()
231#define CPU_IS_PRIMARY(ci) ((ci)->ci_flags & CPUF_PRIMARY)
232#define CPU_IS_RUNNING(ci) ((ci)->ci_flags & CPUF_RUNNING)
233#define cpu_number() (curcpu()->ci_cpuid)
234
235void cpu_unidle(struct cpu_info *);
236void cpu_boot_secondary_processors(void);
237#define cpu_boot_secondary(ci) hw_cpu_boot_secondary(ci)
238#define cpu_hatch(ci) hw_cpu_hatch(ci)
239
240vaddr_t alloc_contiguous_pages(size_t);
241
242#define MIPS64_IPI_NOP 0x00000001
243#define MIPS64_IPI_RENDEZVOUS 0x00000002
244#define MIPS64_IPI_DDB 0x00000004
245#define MIPS64_NIPIS 3 /* must not exceed 32 */
246
247void mips64_ipi_init(void);
248void mips64_send_ipi(unsigned int, unsigned int);
249void smp_rendezvous_cpus(unsigned long, void (*)(void *), void *arg);
250
251#include <sys/mplock.h>
252#else
253#define MAXCPUS 1
254#define curcpu() (&cpu_info_primary)
255#define CPU_IS_PRIMARY(ci) 1
256#define CPU_IS_RUNNING(ci) 1
257#define cpu_number() 0UL
258#define cpu_unidle(ci)
259#define get_cpu_info(i) (&cpu_info_primary)
260#endif
261
262#define CPU_BUSY_CYCLE() __asm volatile ("" ::: "memory")
263
264extern void (*md_initclock)(void);
265extern void (*md_startclock)(struct cpu_info *);
266extern void (*md_triggerclock)(void);
267void cp0_calibrate(struct cpu_info *);
268
269unsigned int cpu_rnd_messybits(void);
270
271#include <machine/frame.h>
272
273/*
274 * Arguments to hardclock encapsulate the previous machine state in
275 * an opaque clockframe.
276 */
277#define clockframe trapframe /* Use normal trap frame */
278
279#define SR_KSU_USER 0x00000010
280#define CLKF_USERMODE(framep) ((framep)->sr & SR_KSU_USER)
281#define CLKF_PC(framep) ((framep)->pc)
282#define CLKF_INTR(framep) (curcpu()->ci_idepth > 1) /* XXX */
283
284/*
285 * This is used during profiling to integrate system time.
286 */
287#define PROC_PC(p) ((p)->p_md.md_regs->pc)
288#define PROC_STACK(p) ((p)->p_md.md_regs->sp)
289
290/*
291 * Preempt the current process if in interrupt from user mode,
292 * or after the current trap/syscall if in system mode.
293 */
294void need_resched(struct cpu_info *);
295#define clear_resched(ci) (ci)->ci_want_resched = 0
296
297/*
298 * Give a profiling tick to the current process when the user profiling
299 * buffer pages are invalid. On MIPS designs, request an ast to send us
300 * through trap, marking the proc as needing a profiling tick.
301 */
302#define need_proftick(p) aston(p)
303
304/*
305 * Notify the current process (p) that it has a signal pending,
306 * process as soon as possible.
307 */
308void signotify(struct proc *);
309
310#define aston(p) ((p)->p_md.md_astpending = 1)
311
312#define mips_sync() __asm__ volatile ("sync" ::: "memory")
313
314#endif /* _KERNEL && !_LOCORE */
315
316#ifdef _KERNEL
317/*
318 * Values for the code field in a break instruction.
319 */
320#define BREAK_INSTR 0x0000000d
321#define BREAK_VAL_MASK 0x03ff0000
322#define BREAK_VAL_SHIFT 16
323#define BREAK_KDB_VAL 512
324#define BREAK_SSTEP_VAL 513
325#define BREAK_BRKPT_VAL 514
326#define BREAK_SOVER_VAL 515
327#define BREAK_DDB_VAL 516
328#define BREAK_FPUEMUL_VAL 517
329#define BREAK_KDB (BREAK_INSTR | (BREAK_KDB_VAL << BREAK_VAL_SHIFT))
330#define BREAK_SSTEP (BREAK_INSTR | (BREAK_SSTEP_VAL << BREAK_VAL_SHIFT))
331#define BREAK_BRKPT (BREAK_INSTR | (BREAK_BRKPT_VAL << BREAK_VAL_SHIFT))
332#define BREAK_SOVER (BREAK_INSTR | (BREAK_SOVER_VAL << BREAK_VAL_SHIFT))
333#define BREAK_DDB (BREAK_INSTR | (BREAK_DDB_VAL << BREAK_VAL_SHIFT))
334#define BREAK_FPUEMUL (BREAK_INSTR | (BREAK_FPUEMUL_VAL << BREAK_VAL_SHIFT))
335
336#endif /* _KERNEL */
337
338/*
339 * CTL_MACHDEP definitions.
340 */
341#define CPU_ALLOWAPERTURE 1 /* allow mmap of /dev/xf86 */
342 /* 2 formerly: keyboard reset */
343 /* 3 formerly: CPU_LIDSUSPEND */
344#define CPU_LIDACTION 4 /* action caused by lid close */
345#define CPU_MAXID 5 /* number of valid machdep ids */
346
347#define CTL_MACHDEP_NAMES { \
348 { 0, 0 }, \
349 { "allowaperture", CTLTYPE_INT }, \
350 { 0, 0 }, \
351 { 0, 0 }, \
352 { "lidaction", CTLTYPE_INT }, \
353}
354
355/*
356 * MIPS CPU types (cp_imp).
357 */
358#define MIPS_R2000 0x01 /* MIPS R2000 CPU ISA I */
359#define MIPS_R3000 0x02 /* MIPS R3000 CPU ISA I */
360#define MIPS_R6000 0x03 /* MIPS R6000 CPU ISA II */
361#define MIPS_R4000 0x04 /* MIPS R4000/4400 CPU ISA III */
362#define MIPS_R3LSI 0x05 /* LSI Logic R3000 derivate ISA I */
363#define MIPS_R6000A 0x06 /* MIPS R6000A CPU ISA II */
364#define MIPS_CN50XX 0x06 /* Cavium OCTEON CN50xx MIPS64R2*/
365#define MIPS_R3IDT 0x07 /* IDT R3000 derivate ISA I */
366#define MIPS_R10000 0x09 /* MIPS R10000/T5 CPU ISA IV */
367#define MIPS_R4200 0x0a /* MIPS R4200 CPU (ICE) ISA III */
368#define MIPS_R4300 0x0b /* NEC VR4300 CPU ISA III */
369#define MIPS_R4100 0x0c /* NEC VR41xx CPU MIPS-16 ISA III */
370#define MIPS_R12000 0x0e /* MIPS R12000 ISA IV */
371#define MIPS_R14000 0x0f /* MIPS R14000 ISA IV */
372#define MIPS_R8000 0x10 /* MIPS R8000 Blackbird/TFP ISA IV */
373#define MIPS_R4600 0x20 /* PMCS R4600 Orion ISA III */
374#define MIPS_R4700 0x21 /* PMCS R4700 Orion ISA III */
375#define MIPS_R3TOSH 0x22 /* Toshiba R3000 based CPU ISA I */
376#define MIPS_R5000 0x23 /* MIPS R5000 CPU ISA IV */
377#define MIPS_RM7000 0x27 /* PMCS RM7000 CPU ISA IV */
378#define MIPS_RM52X0 0x28 /* PMCS RM52X0 CPU ISA IV */
379#define MIPS_RM9000 0x34 /* PMCS RM9000 CPU ISA IV */
380#define MIPS_LOONGSON 0x42 /* STC LoongSon CPU ISA III */
381#define MIPS_VR5400 0x54 /* NEC Vr5400 CPU ISA IV+ */
382#define MIPS_LOONGSON2 0x63 /* STC LoongSon2/3 CPU ISA III+ */
383#define MIPS_CN63XX 0x90 /* Cavium OCTEON II CN6[23]xx MIPS64R2 */
384#define MIPS_CN68XX 0x91 /* Cavium OCTEON II CN68xx MIPS64R2 */
385#define MIPS_CN66XX 0x92 /* Cavium OCTEON II CN66xx MIPS64R2 */
386#define MIPS_CN61XX 0x93 /* Cavium OCTEON II CN6[01]xx MIPS64R2 */
387#define MIPS_CN78XX 0x95 /* Cavium OCTEON III CN7[678]xx MIPS64R2 */
388#define MIPS_CN71XX 0x96 /* Cavium OCTEON III CN7[01]xx MIPS64R2 */
389#define MIPS_CN73XX 0x97 /* Cavium OCTEON III CN7[23]xx MIPS64R2 */
390
391/*
392 * MIPS FPU types. Only soft, rest is the same as cpu type.
393 */
394#define MIPS_SOFT 0x00 /* Software emulation ISA I */
395
396
397#if defined(_KERNEL) && !defined(_LOCORE)
398
399extern register_t protosr;
400extern int cpu_has_synced_cp0_count;
401extern int cpu_has_userlocal;
402
403#ifdef FPUEMUL
404#define CPU_HAS_FPU(ci) ((ci)->ci_hw.c1prid != 0)
405#else
406#define CPU_HAS_FPU(ci) 1
407#endif
408
409struct exec_package;
410struct user;
411
412void tlb_asid_wrap(struct cpu_info *);
413void tlb_flush(int);
414void tlb_flush_addr(vaddr_t);
415void tlb_init(unsigned int);
416void tlb_set_page_mask(uint32_t);
417void tlb_set_pid(u_int);
418void tlb_set_wired(uint32_t);
419int tlb_update(vaddr_t, register_t);
420
421void build_trampoline(vaddr_t, vaddr_t);
422void cpu_switchto_asm(struct proc *, struct proc *);
423int exec_md_map(struct proc *, struct exec_package *);
424void savectx(struct user *, int);
425
426int copyinsn(struct proc *, vaddr_t, uint32_t *);
427void enable_fpu(struct proc *);
428void save_fpu(void);
429int fpe_branch_emulate(struct proc *, struct trapframe *, uint32_t,
430 vaddr_t);
431void MipsSaveCurFPState(struct proc *);
432void MipsSaveCurFPState16(struct proc *);
433void MipsSwitchFPState(struct proc *, struct trapframe *);
434void MipsSwitchFPState16(struct proc *, struct trapframe *);
435
436void MipsFPTrap(struct trapframe *);
437register_t MipsEmulateBranch(struct trapframe *, vaddr_t, uint32_t, uint32_t);
438
439int classify_insn(uint32_t);
440#define INSNCLASS_NEUTRAL 0
441#define INSNCLASS_CALL 1
442#define INSNCLASS_BRANCH 2
443
444/*
445 * Low level access routines to CPU registers
446 */
447
448void setsoftintr0(void);
449void clearsoftintr0(void);
450void setsoftintr1(void);
451void clearsoftintr1(void);
452register_t enableintr(void);
453register_t disableintr(void);
454register_t getsr(void);
455register_t setsr(register_t);
456
457uint32_t cp0_get_cause(void);
458u_int cp0_get_count(void);
459register_t cp0_get_config(void);
460uint32_t cp0_get_config_1(void);
461uint32_t cp0_get_config_2(void);
462uint32_t cp0_get_config_3(void);
463uint32_t cp0_get_config_4(void);
464uint32_t cp0_get_pagegrain(void);
465register_t cp0_get_prid(void);
466void cp0_reset_cause(register_t);
467void cp0_set_compare(u_int);
468void cp0_set_config(register_t);
469void cp0_set_pagegrain(uint32_t);
470void cp0_set_trapbase(register_t);
471u_int cp1_get_prid(void);
472
473static inline uint32_t
474cp0_get_hwrena(void)
475{
476 uint32_t value;
477 __asm__ volatile ("mfc0 %0, $7" : "=r" (value));
478 return value;
479}
480
481static inline void
482cp0_set_hwrena(uint32_t value)
483{
484 __asm__ volatile ("mtc0 %0, $7" : : "r" (value));
485}
486
487static inline void
488cp0_set_userlocal(void *value)
489{
490 __asm__ volatile (
491 " .set push\n"
492 " .set mips64r2\n"
493 " dmtc0 %0, $4, 2\n"
494 " .set pop\n"
495 : : "r" (value));
496}
497
498static inline u_long
499intr_disable(void)
500{
501 return disableintr();
502}
503
504static inline void
505intr_restore(u_long sr)
506{
507 setsr(sr);
508}
509
510/*
511 * Cache routines (may be overridden)
512 */
513
514#ifndef Mips_SyncCache
515#define Mips_SyncCache(ci) \
516 ((ci)->ci_SyncCache)(ci)
517#endif
518#ifndef Mips_InvalidateICache
519#define Mips_InvalidateICache(ci, va, l) \
520 ((ci)->ci_InvalidateICache)(ci, va, l)
521#endif
522#ifndef Mips_InvalidateICachePage
523#define Mips_InvalidateICachePage(ci, va) \
524 ((ci)->ci_InvalidateICachePage)(ci, va)
525#endif
526#ifndef Mips_SyncICache
527#define Mips_SyncICache(ci) \
528 ((ci)->ci_SyncICache)(ci)
529#endif
530#ifndef Mips_SyncDCachePage
531#define Mips_SyncDCachePage(ci, va, pa) \
532 ((ci)->ci_SyncDCachePage)(ci, va, pa)
533#endif
534#ifndef Mips_HitSyncDCachePage
535#define Mips_HitSyncDCachePage(ci, va, pa) \
536 ((ci)->ci_HitSyncDCachePage)(ci, va, pa)
537#endif
538#ifndef Mips_HitSyncDCache
539#define Mips_HitSyncDCache(ci, va, l) \
540 ((ci)->ci_HitSyncDCache)(ci, va, l)
541#endif
542#ifndef Mips_HitInvalidateDCache
543#define Mips_HitInvalidateDCache(ci, va, l) \
544 ((ci)->ci_HitInvalidateDCache)(ci, va, l)
545#endif
546#ifndef Mips_IOSyncDCache
547#define Mips_IOSyncDCache(ci, va, l, h) \
548 ((ci)->ci_IOSyncDCache)(ci, va, l, h)
549#endif
550
551#endif /* _KERNEL && !_LOCORE */
552#endif /* !_MIPS64_CPU_H_ */