1/* $OpenBSD: loongson3.h,v 1.3 2017/05/10 16:04:21 visa Exp $ */
2
3/*
4 * Copyright (c) 2016 Visa Hankala
5 *
6 * Permission to use, copy, modify, and distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
9 *
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 */
18
19#ifndef _MIPS64_LOONGSON3_H_
20#define _MIPS64_LOONGSON3_H_
21
22/*
23 * Definitions for Loongson 3A.
24 */
25
26#define LS3_CFG_BASE(node) (0x100000004000ull*(node) + 0x3ff00000)
27#define LS3_MEM_BASE(node) (0x100000000000ull*(node))
28
29#define LS3_IPI_BASE(n, c) (LS3_CFG_BASE(n) + 0x1000 + 0x100*(c))
30#define LS3_IPI_ISR 0x00
31#define LS3_IPI_IMR 0x04
32#define LS3_IPI_SET 0x08
33#define LS3_IPI_CLEAR 0x0c
34#define LS3_IPI_MBOX0 0x20
35#define LS3_IPI_MBOX1 0x28
36#define LS3_IPI_MBOX2 0x30
37#define LS3_IPI_MBOX3 0x38
38
39static inline uint32_t
40loongson3_get_cpuid(void)
41{
42 uint32_t tmp;
43
44 asm volatile (
45 " .set push\n"
46 " .set mips64\n"
47 " mfc0 %0, $15, 1\n" /* EBase */
48 " .set pop\n"
49 : "=r" (tmp));
50
51 return tmp & 0xf;
52}
53
54#define LS3_COREID(cpuid) ((cpuid) & 3)
55#define LS3_NODEID(cpuid) ((cpuid) >> 2)
56
57/*
58 * Interrupt router registers
59 */
60
61#define LS3_IRT_ENTRY(node, irq) (LS3_CFG_BASE(node) + 0x1400 + (irq))
62#define LS3_IRT_INTISR(node) (LS3_CFG_BASE(node) + 0x1420)
63#define LS3_IRT_INTEN(node) (LS3_CFG_BASE(node) + 0x1424)
64#define LS3_IRT_INTENSET(node) (LS3_CFG_BASE(node) + 0x1428)
65#define LS3_IRT_INTENCLR(node) (LS3_CFG_BASE(node) + 0x142c)
66#define LS3_IRT_INTISR_CORE(node, cpu) (LS3_CFG_BASE(node) + 0x1440 + (cpu)*8)
67
68/* sys int 0-3 */
69#define LS3_IRT_ENTRY_INT(node, x) LS3_IRT_ENTRY((node), (x))
70/* PCI int 0-3 */
71#define LS3_IRT_ENTRY_PCI(node, x) LS3_IRT_ENTRY((node), 0x04+(x))
72/* LPC int */
73#define LS3_IRT_ENTRY_LPC(node) LS3_IRT_ENTRY((node), 0x0a)
74/* HT0 int 0-7 */
75#define LS3_IRT_ENTRY_HT0(node, x) LS3_IRT_ENTRY((node), 0x10+(x))
76/* HT1 int 0-7 */
77#define LS3_IRT_ENTRY_HT1(node, x) LS3_IRT_ENTRY((node), 0x18+(x))
78
79#define LS3_IRT_ROUTE(core, intr) ((0x01 << (core)) | (0x10 << (intr)))
80
81#define LS3_IRQ_INT(x) (x) /* sys int 0-3 */
82#define LS3_IRQ_PCI(x) ((x) + 0x04) /* PCI int 0-3 */
83#define LS3_IRQ_LPC 0x0a /* LPC int */
84#define LS3_IRQ_HT0(x) ((x) + 0x10) /* HT0 int 0-7 */
85#define LS3_IRQ_HT1(x) ((x) + 0x18) /* HT1 int 0-7 */
86#define LS3_IRQ_NUM 32
87
88#define LS3_IRQ_IS_HT(irq) ((irq) >= 0x10)
89
90#define LS3_IRQ_HT_MASK 0xffff0000u
91
92/*
93 * Number of HyperTransport interrupt vectors. In reality, each HT interface
94 * has 256 vectors, but the interrupt code uses only a subset of them.
95 */
96#define LS3_HT_IRQ_NUM 32
97
98/*
99 * HyperTransport registers
100 */
101
102#define LS3_HT1_MEM_BASE(n) (LS3_MEM_BASE(n)+0x00000e0000000000ull)
103#define LS3_HT1_CFG_BASE(n) (LS3_MEM_BASE(n)+0x00000efdfb000000ull)
104
105#define LS3_HT_ISR_OFFSET(x) (0x80 + (x) * 4)
106#define LS3_HT_IMR_OFFSET(x) (0xa0 + (x) * 4)
107
108#endif /* _MIPS64_LOONGSON3_H_ */