1/* $NetBSD: cpu.h,v 1.25 2024/02/28 13:05:39 thorpej Exp $ */
2
3/*
4 * Copyright (c) 1988 University of Utah.
5 * Copyright (c) 1982, 1990, 1993
6 * The Regents of the University of California. All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer
10 * Science Department.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. Neither the name of the University nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
25 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
27 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
30 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
31 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
32 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
33 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * SUCH DAMAGE.
35 *
36 * from: Utah $Hdr: cpu.h 1.16 91/03/25$
37 *
38 * @(#)cpu.h 8.4 (Berkeley) 1/5/94
39 */
40
41#ifndef _M68K_CPU_H_
42#define _M68K_CPU_H_
43
44#if defined(_KERNEL_OPT)
45#include "opt_m68k_arch.h" /* XXX Should not do this here. */
46#endif
47
48/*
49 * Exported definitions common to Motorola m68k-based ports.
50 */
51
52/*
53 * XXX The remaining contents of this file should be split out
54 * XXX into separate files (like m68k.h) and then this file
55 * XXX should go away. Furthermore, most of the stuff defined
56 * XXX here does NOT belong in <machine/cpu.h>, and the ports
57 * XXX using this file should remove <m68k/cpu.h> from there.
58 */
59
60#include <m68k/m68k.h>
61
62/* XXX - Move this stuff into <m68k/cacr.h> maybe? */
63
64/* fields in the 68020 cache control register */
65#define IC_ENABLE 0x0001 /* enable instruction cache */
66#define IC_FREEZE 0x0002 /* freeze instruction cache */
67#define IC_CE 0x0004 /* clear instruction cache entry */
68#define IC_CLR 0x0008 /* clear entire instruction cache */
69
70/* additional fields in the 68030 cache control register */
71#define IC_BE 0x0010 /* instruction burst enable */
72#define DC_ENABLE 0x0100 /* data cache enable */
73#define DC_FREEZE 0x0200 /* data cache freeze */
74#define DC_CE 0x0400 /* clear data cache entry */
75#define DC_CLR 0x0800 /* clear entire data cache */
76#define DC_BE 0x1000 /* data burst enable */
77#define DC_WA 0x2000 /* write allocate */
78
79/* fields in the 68040 cache control register */
80#define IC40_ENABLE 0x00008000 /* instruction cache enable bit */
81#define DC40_ENABLE 0x80000000 /* data cache enable bit */
82
83/* additional fields in the 68060 cache control register */
84#define DC60_NAD 0x40000000 /* no allocate mode, data cache */
85#define DC60_ESB 0x20000000 /* enable store buffer */
86#define DC60_DPI 0x10000000 /* disable CPUSH invalidation */
87#define DC60_FOC 0x08000000 /* four kB data cache mode (else 8) */
88
89#define IC60_EBC 0x00800000 /* enable branch cache */
90#define IC60_CABC 0x00400000 /* clear all branch cache entries */
91#define IC60_CUBC 0x00200000 /* clear user branch cache entries */
92
93#define IC60_NAI 0x00004000 /* no allocate mode, instr. cache */
94#define IC60_FIC 0x00002000 /* four kB instr. cache (else 8) */
95
96#define CACHE_ON (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
97#define CACHE_OFF (DC_CLR|IC_CLR)
98#define CACHE_CLR (CACHE_ON)
99#define IC_CLEAR (DC_WA|DC_BE|DC_ENABLE|IC_BE|IC_CLR|IC_ENABLE)
100#define DC_CLEAR (DC_WA|DC_BE|DC_CLR|DC_ENABLE|IC_BE|IC_ENABLE)
101
102#define CACHE40_ON (IC40_ENABLE|DC40_ENABLE)
103#define CACHE40_OFF (0x00000000)
104
105#define CACHE60_ON (CACHE40_ON|IC60_CABC|IC60_EBC|DC60_ESB)
106#define CACHE60_OFF (CACHE40_OFF|IC60_CABC)
107
108#define CACHELINE_SIZE 16
109#define CACHELINE_MASK (CACHELINE_SIZE - 1)
110
111/* CTL_MACHDEP definitions. (Common to all m68k ports.) */
112#define CPU_CONSDEV 1 /* dev_t: console terminal device */
113#define CPU_ROOT_DEVICE 2 /* string: root device name */
114#define CPU_BOOTED_KERNEL 3 /* string: booted kernel name */
115
116#if defined(_KERNEL) || defined(_KMEMUSER)
117#include <sys/cpu_data.h>
118
119struct cpu_info {
120 struct cpu_data ci_data; /* MI per-cpu data */
121 cpuid_t ci_cpuid;
122 int ci_mtx_count;
123 int ci_mtx_oldspl;
124 volatile int ci_want_resched;
125 volatile int ci_idepth;
126 struct lwp *ci_onproc; /* current user LWP / kthread */
127};
128#endif /* _KERNEL || _KMEMUSER */
129
130#ifdef _KERNEL
131extern struct cpu_info cpu_info_store;
132
133struct proc;
134void cpu_proc_fork(struct proc *, struct proc *);
135
136#define curcpu() (&cpu_info_store)
137
138/*
139 * definitions of cpu-dependent requirements
140 * referenced in generic code
141 */
142#define cpu_number() 0
143
144#define LWP_PC(l) (((struct trapframe *)((l)->l_md.md_regs))->tf_pc)
145
146/*
147 * Arguments to hardclock and gatherstats encapsulate the previous
148 * machine state in an opaque clockframe. On the m68k platforms, we use
149 * what the interrupt stub puts on the stack before calling C code.
150 */
151struct clockframe {
152 /* regs saved on the stack by the interrupt stub */
153 u_int cf_regs[4]; /* d0,d1,a0,a1 */
154 /* hardware frame */
155 u_short cf_sr; /* sr at time of interrupt */
156 u_long cf_pc; /* pc at time of interrupt */
157 u_short cf_vo; /* vector offset (4-word HW frame) */
158} __attribute__((__packed__));
159
160#define CLKF_USERMODE(framep) (((framep)->cf_sr & PSL_S) == 0)
161#define CLKF_PC(framep) ((framep)->cf_pc)
162
163#if 0
164/*
165 * We can determine if we were previously in an interrupt context
166 * if we were running on the interrupt stack (as opposed to the
167 * "master" stack).
168 *
169 * XXX Actually, we can't, because we don't use the master stack
170 * XXX right now.
171 *
172 * (Actually, it's unlikely that we'll ever use the master stack in NetBSD.
173 * It would complicate the spl*() functions considerably and it just doesn't
174 * seem like a good trade-off for what seems like extremely marginal gains.
175 * So, just blissfully run the kernel on the interrupt stack all the time,
176 * and it's been that way for >30 years and no one has really complained
177 * about it.)
178 */
179#define CLKF_INTR(framep) (((framep)->cf_sr & PSL_M) == 0)
180#else
181/*
182 * The clock interrupt handler can determine if it's a nested
183 * interrupt by checking for intr_depth > 1.
184 * (Remember, the clock interrupt handler itself will cause the
185 * depth counter to be incremented).
186 */
187extern volatile unsigned int intr_depth;
188#define CLKF_INTR(framep) (intr_depth > 1)
189#endif
190
191#ifndef __HAVE_M68K_HW_AST
192#define cpu_set_hw_ast(l) __nothing
193#endif
194
195extern volatile int astpending;
196#define cpu_set_ast(l) \
197 do { \
198 __USE(l); astpending = 1; cpu_set_hw_ast(l); \
199 } while (/*CONSTCOND*/0)
200
201/*
202 * Preempt the current process if in interrupt from user mode,
203 * or after the current trap/syscall if in system mode.
204 */
205#define cpu_need_resched(ci, l, flags) \
206 do { \
207 __USE(ci); __USE(flags); cpu_set_ast(l); \
208 } while (/*CONSTCOND*/0)
209
210/*
211 * Give a profiling tick to the current process when the user profiling
212 * buffer pages are invalid. On m68k, request an ast to send us through
213 * trap, marking the proc as needing a profiling tick.
214 */
215#define cpu_need_proftick(l) \
216 do { \
217 (l)->l_pflag |= LP_OWEUPC; cpu_set_ast(l); \
218 } while (/*CONSTCOND*/0)
219
220/*
221 * Notify the current process (p) that it has a signal pending,
222 * process as soon as possible.
223 */
224#define cpu_signotify(l) cpu_set_ast(l)
225
226#endif /* _KERNEL */
227
228#endif /* _M68K_CPU_H_ */