| 1 | /*	$NetBSD: psl.h,v 1.19 2024/01/16 05:29:44 thorpej Exp $	*/ |
| 2 | |
| 3 | /* |
| 4 | * Copyright (c) 1982, 1986, 1993 |
| 5 | *	The Regents of the University of California. All rights reserved. |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * 2. Redistributions in binary form must reproduce the above copyright |
| 13 | * notice, this list of conditions and the following disclaimer in the |
| 14 | * documentation and/or other materials provided with the distribution. |
| 15 | * 3. Neither the name of the University nor the names of its contributors |
| 16 | * may be used to endorse or promote products derived from this software |
| 17 | * without specific prior written permission. |
| 18 | * |
| 19 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
| 20 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 21 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 22 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
| 23 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 24 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 25 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 26 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 27 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 28 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 29 | * SUCH DAMAGE. |
| 30 | * |
| 31 | *	@(#)psl.h	8.1 (Berkeley) 6/10/93 |
| 32 | */ |
| 33 | |
| 34 | #ifndef PSL_C |
| 35 | /* |
| 36 | * MC68000 program status word |
| 37 | */ |
| 38 | |
| 39 | #define	PSL_C		0x0001		/* carry bit */ |
| 40 | #define	PSL_V		0x0002		/* overflow bit */ |
| 41 | #define	PSL_Z		0x0004		/* zero bit */ |
| 42 | #define	PSL_N		0x0008		/* negative bit */ |
| 43 | #define	PSL_X		0x0010		/* extend bit */ |
| 44 | #define	PSL_ALLCC	0x001F		/* all cc bits - unlikely */ |
| 45 | #define	PSL_IPL0	0x0000		/* interrupt priority level 0 */ |
| 46 | #define	PSL_IPL1	0x0100		/* interrupt priority level 1 */ |
| 47 | #define	PSL_IPL2	0x0200		/* interrupt priority level 2 */ |
| 48 | #define	PSL_IPL3	0x0300		/* interrupt priority level 3 */ |
| 49 | #define	PSL_IPL4	0x0400		/* interrupt priority level 4 */ |
| 50 | #define	PSL_IPL5	0x0500		/* interrupt priority level 5 */ |
| 51 | #define	PSL_IPL6	0x0600		/* interrupt priority level 6 */ |
| 52 | #define	PSL_IPL7	0x0700		/* interrupt priority level 7 */ |
| 53 | #define	PSL_M		0x1000		/* master (kernel) sp vs intr sp */ |
| 54 | #define	PSL_S		0x2000		/* supervisor enable bit */ |
| 55 | /*	PSL_T0		0x4000		 ??? T0 on 68020, 8000 is T1 */ |
| 56 | #define	PSL_T		0x8000		/* trace enable bit */ |
| 57 | |
| 58 | #define	PSL_LOWIPL	(PSL_S) |
| 59 | #define	PSL_HIGHIPL	(PSL_S | PSL_IPL7) |
| 60 | #define PSL_IPL		(PSL_IPL7) |
| 61 | #define	PSL_USER	(0) |
| 62 | |
| 63 | #define	PSL_MBZ		0xFFFF58E0	/* must be zero bits */ |
| 64 | |
| 65 | #define	PSL_USERSET	(0) |
| 66 | #define	PSL_USERCLR	(PSL_S | PSL_IPL7 | PSL_MBZ) |
| 67 | |
| 68 | #define	PSLTOIPL(x)	(((x) >> 8) & 0x7) |
| 69 | #define	IPLTOPSL(x)	((((x) & 0x7) << 8) | PSL_S) |
| 70 | |
| 71 | #define	USERMODE(ps)	(((ps) & PSL_S) == 0) |
| 72 | |
| 73 | #if defined(_KERNEL) && !defined(_LOCORE) |
| 74 | |
| 75 | #define	IPL_SAFEPRI	PSL_LOWIPL	/* for kern_sleepq.c */ |
| 76 | |
| 77 | /* |
| 78 | * spl functions; platform-specific code must define spl0 and splx(). |
| 79 | */ |
| 80 | |
| 81 | static inline int |
| 82 | getsr(void) |
| 83 | { |
| 84 | 	int sr; |
| 85 | |
| 86 | 	__asm volatile("clrl %0; movew %%sr,%0" : "=&d" (sr)); |
| 87 | |
| 88 | 	return sr; |
| 89 | } |
| 90 | |
| 91 | static inline int |
| 92 | _spl(int s) |
| 93 | { |
| 94 | 	int sr; |
| 95 | |
| 96 | 	__asm volatile ("clrl %0; movew %%sr,%0; movew %1,%%sr" : |
| 97 | 	 "=&d" (sr) : "di" (s) : "memory"); |
| 98 | |
| 99 | 	return sr; |
| 100 | } |
| 101 | |
| 102 | static inline void |
| 103 | _splx(int s) |
| 104 | { |
| 105 | 	__asm volatile("movew %0,%%sr" : : "di" (s) : "memory"); |
| 106 | } |
| 107 | |
| 108 | static inline int |
| 109 | _splraise(int level) |
| 110 | { |
| 111 | 	int sr; |
| 112 | |
| 113 | 	__asm volatile("clrl %0; movew %%sr,%0" : "=&d" (sr)); |
| 114 | |
| 115 | 	if ((uint16_t)level >= PSL_HIGHIPL || (uint16_t)level > (uint16_t)sr) |
| 116 | 		__asm volatile("movew %0,%%sr" : : "di" (level) : "memory"); |
| 117 | |
| 118 | 	return sr; |
| 119 | } |
| 120 | |
| 121 | /* spl0 may require checking for software interrupts */ |
| 122 | #define	_spl0()		_spl(PSL_S|PSL_IPL0) |
| 123 | #define	spl1()		_spl(PSL_S|PSL_IPL1) |
| 124 | #define	spl2()		_spl(PSL_S|PSL_IPL2) |
| 125 | #define	spl3()		_spl(PSL_S|PSL_IPL3) |
| 126 | #define	spl4()		_spl(PSL_S|PSL_IPL4) |
| 127 | #define	spl5()		_spl(PSL_S|PSL_IPL5) |
| 128 | #define	spl6()		_spl(PSL_S|PSL_IPL6) |
| 129 | #define	spl7()		_spl(PSL_S|PSL_IPL7) |
| 130 | |
| 131 | #define	splraise1()	_splraise(PSL_S|PSL_IPL1) |
| 132 | #define	splraise2()	_splraise(PSL_S|PSL_IPL2) |
| 133 | #define	splraise3()	_splraise(PSL_S|PSL_IPL3) |
| 134 | #define	splraise4()	_splraise(PSL_S|PSL_IPL4) |
| 135 | #define	splraise5()	_splraise(PSL_S|PSL_IPL5) |
| 136 | #define	splraise6()	_splraise(PSL_S|PSL_IPL6) |
| 137 | #define	splraise7()	_splraise(PSL_S|PSL_IPL7) |
| 138 | |
| 139 | #endif /* _KERNEL && ! _LOCORE */ |
| 140 | #endif |