1/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
2/*
3 * Copyright (C) 2001 PPC64 Team, IBM Corp
4 *
5 * This struct defines the way the registers are stored on the
6 * kernel stack during a system call or other kernel entry.
7 *
8 * this should only contain __volatile__ regs
9 * since we can keep non-volatile in the thread_struct
10 * should set this up when only volatiles are saved
11 * by intr code.
12 *
13 * Since this is going on the stack, *CARE MUST BE TAKEN* to insure
14 * that the overall structure is a multiple of 16 bytes in length.
15 *
16 * Note that the offsets of the fields in this struct correspond with
17 * the PT_* values below. This simplifies arch/powerpc/kernel/ptrace.c.
18 *
19 * This program is free software; you can redistribute it and/or
20 * modify it under the terms of the GNU General Public License
21 * as published by the Free Software Foundation; either version
22 * 2 of the License, or (at your option) any later version.
23 */
24#ifndef _ASM_POWERPC_PTRACE_H
25#define _ASM_POWERPC_PTRACE_H
26
27
28#include <linux/types.h>
29
30#ifndef __ASSEMBLER__
31
32struct pt_regs
33{
34 unsigned long gpr[32];
35 unsigned long nip;
36 unsigned long msr;
37 unsigned long orig_gpr3; /* Used for restarting system calls */
38 unsigned long ctr;
39 unsigned long link;
40 unsigned long xer;
41 unsigned long ccr;
42#ifdef __powerpc64__
43 unsigned long softe; /* Soft enabled/disabled */
44#else
45 unsigned long mq; /* 601 only (not used at present) */
46 /* Used on APUS to hold IPL value. */
47#endif
48 unsigned long trap; /* Reason for being here */
49 /* N.B. for critical exceptions on 4xx, the dar and dsisr
50 fields are overloaded to hold srr0 and srr1. */
51 unsigned long dar; /* Fault registers */
52 unsigned long dsisr; /* on 4xx/Book-E used for ESR */
53 unsigned long result; /* Result of a system call */
54};
55
56#endif /* __ASSEMBLER__ */
57
58
59/*
60 * Offsets used by 'ptrace' system call interface.
61 * These can't be changed without breaking binary compatibility
62 * with MkLinux, etc.
63 */
64#define PT_R0 0
65#define PT_R1 1
66#define PT_R2 2
67#define PT_R3 3
68#define PT_R4 4
69#define PT_R5 5
70#define PT_R6 6
71#define PT_R7 7
72#define PT_R8 8
73#define PT_R9 9
74#define PT_R10 10
75#define PT_R11 11
76#define PT_R12 12
77#define PT_R13 13
78#define PT_R14 14
79#define PT_R15 15
80#define PT_R16 16
81#define PT_R17 17
82#define PT_R18 18
83#define PT_R19 19
84#define PT_R20 20
85#define PT_R21 21
86#define PT_R22 22
87#define PT_R23 23
88#define PT_R24 24
89#define PT_R25 25
90#define PT_R26 26
91#define PT_R27 27
92#define PT_R28 28
93#define PT_R29 29
94#define PT_R30 30
95#define PT_R31 31
96
97#define PT_NIP 32
98#define PT_MSR 33
99#define PT_ORIG_R3 34
100#define PT_CTR 35
101#define PT_LNK 36
102#define PT_XER 37
103#define PT_CCR 38
104#ifndef __powerpc64__
105#define PT_MQ 39
106#else
107#define PT_SOFTE 39
108#endif
109#define PT_TRAP 40
110#define PT_DAR 41
111#define PT_DSISR 42
112#define PT_RESULT 43
113#define PT_DSCR 44
114#define PT_REGS_COUNT 44
115
116#define PT_FPR0 48 /* each FP reg occupies 2 slots in this space */
117
118#ifndef __powerpc64__
119
120#define PT_FPR31 (PT_FPR0 + 2*31)
121#define PT_FPSCR (PT_FPR0 + 2*32 + 1)
122
123#else /* __powerpc64__ */
124
125#define PT_FPSCR (PT_FPR0 + 32) /* each FP reg occupies 1 slot in 64-bit space */
126
127
128#define PT_VR0 82 /* each Vector reg occupies 2 slots in 64-bit */
129#define PT_VSCR (PT_VR0 + 32*2 + 1)
130#define PT_VRSAVE (PT_VR0 + 33*2)
131
132
133/*
134 * Only store first 32 VSRs here. The second 32 VSRs in VR0-31
135 */
136#define PT_VSR0 150 /* each VSR reg occupies 2 slots in 64-bit */
137#define PT_VSR31 (PT_VSR0 + 2*31)
138#endif /* __powerpc64__ */
139
140/*
141 * Get/set all the altivec registers v0..v31, vscr, vrsave, in one go.
142 * The transfer totals 34 quadword. Quadwords 0-31 contain the
143 * corresponding vector registers. Quadword 32 contains the vscr as the
144 * last word (offset 12) within that quadword. Quadword 33 contains the
145 * vrsave as the first word (offset 0) within the quadword.
146 *
147 * This definition of the VMX state is compatible with the current PPC32
148 * ptrace interface. This allows signal handling and ptrace to use the same
149 * structures. This also simplifies the implementation of a bi-arch
150 * (combined (32- and 64-bit) gdb.
151 */
152#define PTRACE_GETVRREGS 0x12
153#define PTRACE_SETVRREGS 0x13
154
155/* Get/set all the upper 32-bits of the SPE registers, accumulator, and
156 * spefscr, in one go */
157#define PTRACE_GETEVRREGS 0x14
158#define PTRACE_SETEVRREGS 0x15
159
160/* Get the first 32 128bit VSX registers */
161#define PTRACE_GETVSRREGS 0x1b
162#define PTRACE_SETVSRREGS 0x1c
163
164/* Syscall emulation defines */
165#define PTRACE_SYSEMU 0x1d
166#define PTRACE_SYSEMU_SINGLESTEP 0x1e
167
168/*
169 * Get or set a debug register. The first 16 are DABR registers and the
170 * second 16 are IABR registers.
171 */
172#define PTRACE_GET_DEBUGREG 0x19
173#define PTRACE_SET_DEBUGREG 0x1a
174
175/* (new) PTRACE requests using the same numbers as x86 and the same
176 * argument ordering. Additionally, they support more registers too
177 */
178#define PTRACE_GETREGS 0xc
179#define PTRACE_SETREGS 0xd
180#define PTRACE_GETFPREGS 0xe
181#define PTRACE_SETFPREGS 0xf
182#define PTRACE_GETREGS64 0x16
183#define PTRACE_SETREGS64 0x17
184
185/* Calls to trace a 64bit program from a 32bit program */
186#define PPC_PTRACE_PEEKTEXT_3264 0x95
187#define PPC_PTRACE_PEEKDATA_3264 0x94
188#define PPC_PTRACE_POKETEXT_3264 0x93
189#define PPC_PTRACE_POKEDATA_3264 0x92
190#define PPC_PTRACE_PEEKUSR_3264 0x91
191#define PPC_PTRACE_POKEUSR_3264 0x90
192
193#define PTRACE_SINGLEBLOCK 0x100 /* resume execution until next branch */
194
195#define PPC_PTRACE_GETHWDBGINFO 0x89
196#define PPC_PTRACE_SETHWDEBUG 0x88
197#define PPC_PTRACE_DELHWDEBUG 0x87
198
199#ifndef __ASSEMBLER__
200
201struct ppc_debug_info {
202 __u32 version; /* Only version 1 exists to date */
203 __u32 num_instruction_bps;
204 __u32 num_data_bps;
205 __u32 num_condition_regs;
206 __u32 data_bp_alignment;
207 __u32 sizeof_condition; /* size of the DVC register */
208 __u64 features;
209};
210
211#endif /* __ASSEMBLER__ */
212
213/*
214 * features will have bits indication whether there is support for:
215 */
216#define PPC_DEBUG_FEATURE_INSN_BP_RANGE 0x0000000000000001
217#define PPC_DEBUG_FEATURE_INSN_BP_MASK 0x0000000000000002
218#define PPC_DEBUG_FEATURE_DATA_BP_RANGE 0x0000000000000004
219#define PPC_DEBUG_FEATURE_DATA_BP_MASK 0x0000000000000008
220#define PPC_DEBUG_FEATURE_DATA_BP_DAWR 0x0000000000000010
221#define PPC_DEBUG_FEATURE_DATA_BP_ARCH_31 0x0000000000000020
222
223#ifndef __ASSEMBLER__
224
225struct ppc_hw_breakpoint {
226 __u32 version; /* currently, version must be 1 */
227 __u32 trigger_type; /* only some combinations allowed */
228 __u32 addr_mode; /* address match mode */
229 __u32 condition_mode; /* break/watchpoint condition flags */
230 __u64 addr; /* break/watchpoint address */
231 __u64 addr2; /* range end or mask */
232 __u64 condition_value; /* contents of the DVC register */
233};
234
235#endif /* __ASSEMBLER__ */
236
237/*
238 * Trigger Type
239 */
240#define PPC_BREAKPOINT_TRIGGER_EXECUTE 0x00000001
241#define PPC_BREAKPOINT_TRIGGER_READ 0x00000002
242#define PPC_BREAKPOINT_TRIGGER_WRITE 0x00000004
243#define PPC_BREAKPOINT_TRIGGER_RW \
244 (PPC_BREAKPOINT_TRIGGER_READ | PPC_BREAKPOINT_TRIGGER_WRITE)
245
246/*
247 * Address Mode
248 */
249#define PPC_BREAKPOINT_MODE_EXACT 0x00000000
250#define PPC_BREAKPOINT_MODE_RANGE_INCLUSIVE 0x00000001
251#define PPC_BREAKPOINT_MODE_RANGE_EXCLUSIVE 0x00000002
252#define PPC_BREAKPOINT_MODE_MASK 0x00000003
253
254/*
255 * Condition Mode
256 */
257#define PPC_BREAKPOINT_CONDITION_MODE 0x00000003
258#define PPC_BREAKPOINT_CONDITION_NONE 0x00000000
259#define PPC_BREAKPOINT_CONDITION_AND 0x00000001
260#define PPC_BREAKPOINT_CONDITION_EXACT PPC_BREAKPOINT_CONDITION_AND
261#define PPC_BREAKPOINT_CONDITION_OR 0x00000002
262#define PPC_BREAKPOINT_CONDITION_AND_OR 0x00000003
263#define PPC_BREAKPOINT_CONDITION_BE_ALL 0x00ff0000
264#define PPC_BREAKPOINT_CONDITION_BE_SHIFT 16
265#define PPC_BREAKPOINT_CONDITION_BE(n) \
266 (1<<((n)+PPC_BREAKPOINT_CONDITION_BE_SHIFT))
267
268#endif /* _ASM_POWERPC_PTRACE_H */