1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#ifndef _FENV_H_
30#define _FENV_H_
31
32#include <sys/_types.h>
33#include <machine/endian.h>
34
35#ifndef __fenv_static
36#define __fenv_static static
37#endif
38
39typedef __uint32_t fenv_t;
40typedef __uint32_t fexcept_t;
41
42/* Exception flags */
43#ifdef __SPE__
44#define FE_OVERFLOW 0x00000100
45#define FE_UNDERFLOW 0x00000200
46#define FE_DIVBYZERO 0x00000400
47#define FE_INVALID 0x00000800
48#define FE_INEXACT 0x00001000
49
50#define FE_ALL_INVALID FE_INVALID
51
52#define _FPUSW_SHIFT 6
53#else
54#define FE_INEXACT 0x02000000
55#define FE_DIVBYZERO 0x04000000
56#define FE_UNDERFLOW 0x08000000
57#define FE_OVERFLOW 0x10000000
58#define FE_INVALID 0x20000000 /* all types of invalid FP ops */
59
60/*
61 * The PowerPC architecture has extra invalid flags that indicate the
62 * specific type of invalid operation occurred. These flags may be
63 * tested, set, and cleared---but not masked---separately. All of
64 * these bits are cleared when FE_INVALID is cleared, but only
65 * FE_VXSOFT is set when FE_INVALID is explicitly set in software.
66 */
67#define FE_VXCVI 0x00000100 /* invalid integer convert */
68#define FE_VXSQRT 0x00000200 /* square root of a negative */
69#define FE_VXSOFT 0x00000400 /* software-requested exception */
70#define FE_VXVC 0x00080000 /* ordered comparison involving NaN */
71#define FE_VXIMZ 0x00100000 /* inf * 0 */
72#define FE_VXZDZ 0x00200000 /* 0 / 0 */
73#define FE_VXIDI 0x00400000 /* inf / inf */
74#define FE_VXISI 0x00800000 /* inf - inf */
75#define FE_VXSNAN 0x01000000 /* operation on a signalling NaN */
76#define FE_ALL_INVALID (FE_VXCVI | FE_VXSQRT | FE_VXSOFT | FE_VXVC | \
77 FE_VXIMZ | FE_VXZDZ | FE_VXIDI | FE_VXISI | \
78 FE_VXSNAN | FE_INVALID)
79
80#define _FPUSW_SHIFT 22
81#endif
82#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \
83 FE_ALL_INVALID | FE_OVERFLOW | FE_UNDERFLOW)
84
85/* Rounding modes */
86#define FE_TONEAREST 0x0000
87#define FE_TOWARDZERO 0x0001
88#define FE_UPWARD 0x0002
89#define FE_DOWNWARD 0x0003
90#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \
91 FE_UPWARD | FE_TOWARDZERO)
92
93__BEGIN_DECLS
94
95/* Default floating-point environment */
96extern const fenv_t __fe_dfl_env;
97#define FE_DFL_ENV (&__fe_dfl_env)
98
99/* We need to be able to map status flag positions to mask flag positions */
100#define _ENABLE_MASK ((FE_DIVBYZERO | FE_INEXACT | FE_INVALID | \
101 FE_OVERFLOW | FE_UNDERFLOW) >> _FPUSW_SHIFT)
102
103#ifndef _SOFT_FLOAT
104#ifdef __SPE__
105#define __mffs(__env) \
106 __asm __volatile("mfspr %0, 512" : "=r" ((__env)->__bits.__reg))
107#define __mtfsf(__env) \
108 __asm __volatile("mtspr 512,%0;isync" :: "r" ((__env).__bits.__reg))
109#else
110#define __mffs(__env) \
111 __asm __volatile("mffs %0" : "=f" ((__env)->__d))
112#define __mtfsf(__env) \
113 __asm __volatile("mtfsf 255,%0" :: "f" ((__env).__d))
114#endif
115#else
116#define __mffs(__env)
117#define __mtfsf(__env)
118#endif
119
120union __fpscr {
121 double __d;
122 struct {
123#if _BYTE_ORDER == _LITTLE_ENDIAN
124 fenv_t __reg;
125 __uint32_t __junk;
126#else
127 __uint32_t __junk;
128 fenv_t __reg;
129#endif
130 } __bits;
131};
132
133__fenv_static inline int
134feclearexcept(int __excepts)
135{
136 union __fpscr __r;
137
138 if (__excepts & FE_INVALID)
139 __excepts |= FE_ALL_INVALID;
140 __mffs(&__r);
141 __r.__bits.__reg &= ~__excepts;
142 __mtfsf(__r);
143 return (0);
144}
145
146__fenv_static inline int
147fegetexceptflag(fexcept_t *__flagp, int __excepts)
148{
149 union __fpscr __r;
150
151 __mffs(&__r);
152 *__flagp = __r.__bits.__reg & __excepts;
153 return (0);
154}
155
156__fenv_static inline int
157fesetexceptflag(const fexcept_t *__flagp, int __excepts)
158{
159 union __fpscr __r;
160
161 if (__excepts & FE_INVALID)
162 __excepts |= FE_ALL_INVALID;
163 __mffs(&__r);
164 __r.__bits.__reg &= ~__excepts;
165 __r.__bits.__reg |= *__flagp & __excepts;
166 __mtfsf(__r);
167 return (0);
168}
169
170#ifdef __SPE__
171extern int feraiseexcept(int __excepts);
172#else
173__fenv_static inline int
174feraiseexcept(int __excepts)
175{
176 union __fpscr __r;
177
178 if (__excepts & FE_INVALID)
179 __excepts |= FE_VXSOFT;
180 __mffs(&__r);
181 __r.__bits.__reg |= __excepts;
182 __mtfsf(__r);
183 return (0);
184}
185#endif
186
187__fenv_static inline int
188fetestexcept(int __excepts)
189{
190 union __fpscr __r;
191
192 __mffs(&__r);
193 return (__r.__bits.__reg & __excepts);
194}
195
196__fenv_static inline int
197fegetround(void)
198{
199 union __fpscr __r;
200
201 __mffs(&__r);
202 return (__r.__bits.__reg & _ROUND_MASK);
203}
204
205__fenv_static inline int
206fesetround(int __round)
207{
208 union __fpscr __r;
209
210 if (__round & ~_ROUND_MASK)
211 return (-1);
212 __mffs(&__r);
213 __r.__bits.__reg &= ~_ROUND_MASK;
214 __r.__bits.__reg |= __round;
215 __mtfsf(__r);
216 return (0);
217}
218
219__fenv_static inline int
220fegetenv(fenv_t *__envp)
221{
222 union __fpscr __r;
223
224 __mffs(&__r);
225 *__envp = __r.__bits.__reg;
226 return (0);
227}
228
229__fenv_static inline int
230feholdexcept(fenv_t *__envp)
231{
232 union __fpscr __r;
233
234 __mffs(&__r);
235 *__envp = __r.__bits.__reg;
236 __r.__bits.__reg &= ~(FE_ALL_EXCEPT | _ENABLE_MASK);
237 __mtfsf(__r);
238 return (0);
239}
240
241__fenv_static inline int
242fesetenv(const fenv_t *__envp)
243{
244 union __fpscr __r;
245
246 __r.__bits.__reg = *__envp;
247 __mtfsf(__r);
248 return (0);
249}
250
251__fenv_static inline int
252feupdateenv(const fenv_t *__envp)
253{
254 union __fpscr __r;
255
256 __mffs(&__r);
257 __r.__bits.__reg &= FE_ALL_EXCEPT;
258 __r.__bits.__reg |= *__envp;
259 __mtfsf(__r);
260 return (0);
261}
262
263#if __BSD_VISIBLE
264
265__fenv_static inline int
266feenableexcept(int __mask)
267{
268 union __fpscr __r;
269 fenv_t __oldmask;
270
271 __mffs(&__r);
272 __oldmask = __r.__bits.__reg;
273 __r.__bits.__reg |= (__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT;
274 __mtfsf(__r);
275 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
276}
277
278__fenv_static inline int
279fedisableexcept(int __mask)
280{
281 union __fpscr __r;
282 fenv_t __oldmask;
283
284 __mffs(&__r);
285 __oldmask = __r.__bits.__reg;
286 __r.__bits.__reg &= ~((__mask & FE_ALL_EXCEPT) >> _FPUSW_SHIFT);
287 __mtfsf(__r);
288 return ((__oldmask & _ENABLE_MASK) << _FPUSW_SHIFT);
289}
290
291/* We currently provide no external definition of fegetexcept(). */
292static inline int
293fegetexcept(void)
294{
295 union __fpscr __r;
296
297 __mffs(&__r);
298 return ((__r.__bits.__reg & _ENABLE_MASK) << _FPUSW_SHIFT);
299}
300
301#endif /* __BSD_VISIBLE */
302
303__END_DECLS
304
305#endif /* !_FENV_H_ */