1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 1999 Luoqi Chen <luoqi@freebsd.org>
5 * Copyright (c) Peter Wemm <peter@netplex.com.au>
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27 * SUCH DAMAGE.
28 */
29
30#ifndef _MACHINE_PCPU_H_
31#define _MACHINE_PCPU_H_
32
33#include <machine/cpufunc.h>
34#include <machine/slb.h>
35#include <machine/tlb.h>
36
37struct pmap;
38struct pvo_entry;
39#define CPUSAVE_LEN 9
40
41#define PCPU_MD_COMMON_FIELDS \
42 int pc_inside_intr; \
43 struct pmap *pc_curpmap; /* current pmap */ \
44 struct thread *pc_fputhread; /* current fpu user */ \
45 struct thread *pc_vecthread; /* current vec user */ \
46 struct thread *pc_htmthread; /* current htm user */ \
47 uintptr_t pc_hwref; \
48 int pc_bsp; \
49 volatile int pc_awake; \
50 uint32_t pc_ipimask; \
51 uint32_t pc_flags; /* cpu feature flags */ \
52 register_t pc_tempsave[CPUSAVE_LEN]; \
53 register_t pc_disisave[CPUSAVE_LEN]; \
54 register_t pc_dbsave[CPUSAVE_LEN]; \
55 void *pc_restore; \
56 vm_offset_t pc_qmap_addr;
57
58#define PCPU_MD_AIM32_FIELDS \
59 struct pvo_entry *qmap_pvo; \
60 struct mtx qmap_lock; \
61 char __pad[128];
62
63#define PCPU_MD_AIM64_FIELDS \
64 struct slb slb[64]; \
65 struct slb **userslb; \
66 register_t slbsave[18]; \
67 uint8_t slbstack[1024]; \
68 struct pvo_entry *qmap_pvo; \
69 struct mtx qmap_lock; \
70 uint64_t opal_hmi_flags; \
71 char __pad[1337];
72
73#ifdef __powerpc64__
74#define PCPU_MD_AIM_FIELDS PCPU_MD_AIM64_FIELDS
75#else
76#define PCPU_MD_AIM_FIELDS PCPU_MD_AIM32_FIELDS
77#endif
78
79/* CPU feature flags, can be used for cached flow control. */
80#define PC_FLAG_NOSRS 0x80000000
81
82#define BOOKE_CRITSAVE_LEN (CPUSAVE_LEN + 2)
83#define BOOKE_TLB_MAXNEST 4
84#define BOOKE_TLB_SAVELEN 16
85#define BOOKE_TLBSAVE_LEN (BOOKE_TLB_SAVELEN * BOOKE_TLB_MAXNEST)
86
87#ifdef __powerpc64__
88#define BOOKE_PCPU_PAD 901
89#else
90#define BOOKE_PCPU_PAD 365
91#endif
92#define PCPU_MD_BOOKE_FIELDS \
93 register_t critsave[BOOKE_CRITSAVE_LEN]; \
94 register_t mchksave[CPUSAVE_LEN]; \
95 register_t tlbsave[BOOKE_TLBSAVE_LEN]; \
96 register_t tlb_level; \
97 uintptr_t *tlb_lock; \
98 int tid_next; \
99 char __pad[BOOKE_PCPU_PAD];
100
101/* Definitions for register offsets within the exception tmp save areas */
102#define CPUSAVE_R27 0 /* where r27 gets saved */
103#define CPUSAVE_R28 1 /* where r28 gets saved */
104#define CPUSAVE_R29 2 /* where r29 gets saved */
105#define CPUSAVE_R30 3 /* where r30 gets saved */
106#define CPUSAVE_R31 4 /* where r31 gets saved */
107#define CPUSAVE_AIM_DAR 5 /* where SPR_DAR gets saved */
108#define CPUSAVE_AIM_DSISR 6 /* where SPR_DSISR gets saved */
109#define CPUSAVE_BOOKE_DEAR 5 /* where SPR_DEAR gets saved */
110#define CPUSAVE_BOOKE_ESR 6 /* where SPR_ESR gets saved */
111#define CPUSAVE_SRR0 7 /* where SRR0 gets saved */
112#define CPUSAVE_SRR1 8 /* where SRR1 gets saved */
113#define BOOKE_CRITSAVE_SRR0 9 /* where real SRR0 gets saved (critical) */
114#define BOOKE_CRITSAVE_SRR1 10 /* where real SRR0 gets saved (critical) */
115
116/* Book-E TLBSAVE is more elaborate */
117#define TLBSAVE_BOOKE_LR 0
118#define TLBSAVE_BOOKE_CR 1
119#define TLBSAVE_BOOKE_SRR0 2
120#define TLBSAVE_BOOKE_SRR1 3
121#define TLBSAVE_BOOKE_R20 4
122#define TLBSAVE_BOOKE_R21 5
123#define TLBSAVE_BOOKE_R22 6
124#define TLBSAVE_BOOKE_R23 7
125#define TLBSAVE_BOOKE_R24 8
126#define TLBSAVE_BOOKE_R25 9
127#define TLBSAVE_BOOKE_R26 10
128#define TLBSAVE_BOOKE_R27 11
129#define TLBSAVE_BOOKE_R28 12
130#define TLBSAVE_BOOKE_R29 13
131#define TLBSAVE_BOOKE_R30 14
132#define TLBSAVE_BOOKE_R31 15
133
134#define PCPU_MD_FIELDS \
135 PCPU_MD_COMMON_FIELDS \
136 union { \
137 struct { \
138 PCPU_MD_AIM_FIELDS \
139 } pc_aim; \
140 struct { \
141 PCPU_MD_BOOKE_FIELDS \
142 } pc_booke; \
143 }
144
145#ifdef _KERNEL
146
147#define pcpup (get_pcpu())
148
149static __inline __pure2 struct thread *
150__curthread(void)
151{
152 struct thread *td;
153#ifdef __powerpc64__
154 __asm __volatile("mr %0,13" : "=r"(td));
155#else
156 __asm __volatile("mr %0,2" : "=r"(td));
157#endif
158 return (td);
159}
160#define curthread (__curthread())
161
162#define PCPU_GET(member) (pcpup->pc_ ## member)
163
164/*
165 * XXX The implementation of this operation should be made atomic
166 * with respect to preemption.
167 */
168#define PCPU_ADD(member, value) (pcpup->pc_ ## member += (value))
169#define PCPU_PTR(member) (&pcpup->pc_ ## member)
170#define PCPU_SET(member,value) (pcpup->pc_ ## member = (value))
171
172#endif /* _KERNEL */
173
174#endif /* !_MACHINE_PCPU_H_ */