1/*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
5 * Copyright (C) 1995, 1996 TooLs GmbH.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by TooLs GmbH.
19 * 4. The name of TooLs GmbH may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $NetBSD: psl.h,v 1.5 2000/11/19 19:52:37 matt Exp $
34 */
35
36#ifndef _MACHINE_PSL_H_
37#define _MACHINE_PSL_H_
38
39/*
40 * Machine State Register (MSR) - All cores
41 */
42#define PSL_VEC 0x02000000UL /* AltiVec/SPE vector unit available */
43#define PSL_VSX 0x00800000UL /* Vector-Scalar unit available */
44#define PSL_EE 0x00008000UL /* external interrupt enable */
45#define PSL_PR 0x00004000UL /* privilege mode (1 == user) */
46#define PSL_FP 0x00002000UL /* floating point enable */
47#define PSL_ME 0x00001000UL /* machine check enable */
48#define PSL_FE0 0x00000800UL /* floating point interrupt mode 0 */
49#define PSL_FE1 0x00000100UL /* floating point interrupt mode 1 */
50#define PSL_PMM 0x00000004UL /* performance monitor mark */
51#define PSL_RI 0x00000002UL /* recoverable interrupt */
52
53/* Machine State Register - Book-E cores */
54#ifdef __powerpc64__
55#define PSL_CM 0x80000000UL /* Computation Mode (64-bit) */
56#endif
57
58#define PSL_GS 0x10000000UL /* Guest state */
59#define PSL_UCLE 0x04000000UL /* User mode cache lock enable */
60#define PSL_WE 0x00040000UL /* Wait state enable */
61#define PSL_CE 0x00020000UL /* Critical interrupt enable */
62#define PSL_UBLE 0x00000400UL /* BTB lock enable - e500 only */
63#define PSL_DWE 0x00000400UL /* Debug Wait Enable - 440 only*/
64#define PSL_DE 0x00000200UL /* Debug interrupt enable */
65#define PSL_IS 0x00000020UL /* Instruction address space */
66#define PSL_DS 0x00000010UL /* Data address space */
67
68/* Machine State Register (MSR) - AIM cores */
69#ifdef __powerpc64__
70#define PSL_SF 0x8000000000000000UL /* 64-bit addressing */
71#define PSL_HV 0x1000000000000000UL /* hyper-privileged mode */
72#endif
73
74#define PSL_POW 0x00040000UL /* power management */
75#define PSL_ILE 0x00010000UL /* interrupt endian mode (1 == le) */
76#define PSL_SE 0x00000400UL /* single-step trace enable */
77#define PSL_BE 0x00000200UL /* branch trace enable */
78#define PSL_IP 0x00000040UL /* interrupt prefix - 601 only */
79#define PSL_IR 0x00000020UL /* instruction address relocation */
80#define PSL_DR 0x00000010UL /* data address relocation */
81#define PSL_LE 0x00000001UL /* endian mode (1 == le) */
82
83/*
84 * Floating-point exception modes:
85 */
86#define PSL_FE_DIS 0 /* none */
87#define PSL_FE_NONREC PSL_FE1 /* imprecise non-recoverable */
88#define PSL_FE_REC PSL_FE0 /* imprecise recoverable */
89#define PSL_FE_PREC (PSL_FE0 | PSL_FE1) /* precise */
90#define PSL_FE_DFLT PSL_FE_PREC /* default == precise */
91
92#ifndef LOCORE
93extern register_t psl_kernset; /* Default MSR values for kernel */
94extern register_t psl_userset; /* Default MSR values for userland */
95#ifdef __powerpc64__
96extern register_t psl_userset32; /* Default user MSR values for 32-bit */
97#endif
98extern register_t psl_userstatic; /* Bits of SRR1 userland may not set */
99#endif
100
101#endif /* _MACHINE_PSL_H_ */