1/*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
5 * Copyright (C) 1995, 1996 TooLs GmbH.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by TooLs GmbH.
19 * 4. The name of TooLs GmbH may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 * $NetBSD: pte.h,v 1.2 1998/08/31 14:43:40 tsubai Exp $
34 */
35
36#ifndef _MACHINE_PTE_H_
37#define _MACHINE_PTE_H_
38
39#if defined(AIM)
40
41/*
42 * Page Table Entries
43 */
44#ifndef LOCORE
45
46/* 32-bit PTE */
47struct pte {
48 u_int32_t pte_hi;
49 u_int32_t pte_lo;
50};
51
52struct pteg {
53 struct pte pt[8];
54};
55
56/* 64-bit (long) PTE */
57struct lpte {
58 u_int64_t pte_hi;
59 u_int64_t pte_lo;
60};
61
62struct lpteg {
63 struct lpte pt[8];
64};
65
66/* Partition table entry */
67struct pate {
68 u_int64_t pagetab;
69 u_int64_t proctab;
70};
71
72/* Process table entry */
73struct prte {
74 u_int64_t proctab0;
75 u_int64_t proctab1;
76};
77
78typedef struct pte pte_t;
79typedef struct lpte lpte_t;
80#endif /* LOCORE */
81
82/* 32-bit PTE definitions */
83
84/* High word: */
85#define PTE_VALID 0x80000000
86#define PTE_VSID_SHFT 7
87#define PTE_HID 0x00000040
88#define PTE_API 0x0000003f
89/* Low word: */
90#define PTE_RPGN 0xfffff000
91#define PTE_REF 0x00000100
92#define PTE_CHG 0x00000080
93#define PTE_WIMG 0x00000078
94#define PTE_W 0x00000040
95#define PTE_I 0x00000020
96#define PTE_M 0x00000010
97#define PTE_G 0x00000008
98#define PTE_PP 0x00000003
99#define PTE_SO 0x00000000 /* Super. Only (U: XX, S: RW) */
100#define PTE_SW 0x00000001 /* Super. Write-Only (U: RO, S: RW) */
101#define PTE_BW 0x00000002 /* Supervisor (U: RW, S: RW) */
102#define PTE_BR 0x00000003 /* Both Read Only (U: RO, S: RO) */
103#define PTE_RW PTE_BW
104#define PTE_RO PTE_BR
105
106#define PTE_EXEC 0x00000200 /* pseudo bit in attrs; page is exec */
107
108/* 64-bit PTE definitions */
109
110/* High quadword: */
111#define LPTE_VSID_SHIFT 12
112#define LPTE_AVPN_MASK 0xFFFFFFFFFFFFFF80ULL
113#define LPTE_AVA_MASK 0x3FFFFFFFFFFFFF80ULL
114#define LPTE_API 0x0000000000000F80ULL
115#define LPTE_SWBITS 0x0000000000000078ULL
116#define LPTE_WIRED 0x0000000000000010ULL
117#define LPTE_LOCKED 0x0000000000000008ULL
118#define LPTE_BIG 0x0000000000000004ULL /* 4kb/16Mb page */
119#define LPTE_HID 0x0000000000000002ULL
120#define LPTE_VALID 0x0000000000000001ULL
121
122/* Low quadword: */
123#define LP_4K_16M 0x38 /* 4KB base, 16MB actual page size */
124
125#define EXTEND_PTE(x) UINT64_C(x) /* make constants 64-bit */
126#define LPTE_RPGN 0xfffffffffffff000ULL
127#define LPTE_LP_MASK 0x00000000000ff000ULL
128#define LPTE_LP_SHIFT 12
129#define LPTE_LP_4K_16M ((unsigned long long)(LP_4K_16M) << LPTE_LP_SHIFT)
130#define LPTE_REF EXTEND_PTE( PTE_REF )
131#define LPTE_CHG EXTEND_PTE( PTE_CHG )
132#define LPTE_WIMG EXTEND_PTE( PTE_WIMG )
133#define LPTE_W EXTEND_PTE( PTE_W )
134#define LPTE_I EXTEND_PTE( PTE_I )
135#define LPTE_M EXTEND_PTE( PTE_M )
136#define LPTE_G EXTEND_PTE( PTE_G )
137#define LPTE_NOEXEC 0x0000000000000004ULL
138#define LPTE_PP EXTEND_PTE( PTE_PP )
139
140#define LPTE_SO EXTEND_PTE( PTE_SO ) /* Super. Only */
141#define LPTE_SW EXTEND_PTE( PTE_SW ) /* Super. Write-Only */
142#define LPTE_BW EXTEND_PTE( PTE_BW ) /* Supervisor */
143#define LPTE_BR EXTEND_PTE( PTE_BR ) /* Both Read Only */
144#define LPTE_RW LPTE_BW
145#define LPTE_RO LPTE_BR
146
147/* HPT superpage definitions */
148#define HPT_SP_SHIFT (VM_LEVEL_0_ORDER + PAGE_SHIFT)
149#define HPT_SP_SIZE (1 << HPT_SP_SHIFT)
150#define HPT_SP_MASK (HPT_SP_SIZE - 1)
151#define HPT_SP_PAGES (1 << VM_LEVEL_0_ORDER)
152
153/* POWER ISA 3.0 Radix Table Definitions */
154#define RPTE_VALID 0x8000000000000000ULL
155#define RPTE_LEAF 0x4000000000000000ULL /* is a PTE: always 1 */
156#define RPTE_SW0 0x2000000000000000ULL
157#define RPTE_RPN_MASK 0x00FFFFFFFFFFF000ULL
158#define RPTE_RPN_SHIFT 12
159#define RPTE_SW1 0x0000000000000800ULL
160#define RPTE_SW2 0x0000000000000400ULL
161#define RPTE_SW3 0x0000000000000200ULL
162#define RPTE_R 0x0000000000000100ULL
163#define RPTE_C 0x0000000000000080ULL
164
165#define RPTE_MANAGED RPTE_SW1
166#define RPTE_WIRED RPTE_SW2
167#define RPTE_PROMOTED RPTE_SW3
168
169#define RPTE_ATTR_MASK 0x0000000000000030ULL
170#define RPTE_ATTR_MEM 0x0000000000000000ULL /* PTE M */
171#define RPTE_ATTR_SAO 0x0000000000000010ULL /* PTE WIM */
172#define RPTE_ATTR_GUARDEDIO 0x0000000000000020ULL /* PTE IMG */
173#define RPTE_ATTR_UNGUARDEDIO 0x0000000000000030ULL /* PTE IM */
174
175#define RPTE_EAA_MASK 0x000000000000000FULL
176#define RPTE_EAA_P 0x0000000000000008ULL /* Supervisor only */
177#define RPTE_EAA_R 0x0000000000000004ULL /* Read allowed */
178#define RPTE_EAA_W 0x0000000000000002ULL /* Write (+read) */
179#define RPTE_EAA_X 0x0000000000000001ULL /* Execute allowed */
180
181#define RPDE_VALID RPTE_VALID
182#define RPDE_LEAF RPTE_LEAF /* is a PTE: always 0 */
183#define RPDE_NLB_MASK 0x00FFFFFFFFFFFF00ULL
184#define RPDE_NLB_SHIFT 8
185#define RPDE_NLS_MASK 0x000000000000001FULL
186
187#define PG_FRAME (0x000ffffffffff000ul)
188#define PG_PS_FRAME (0x000fffffffe00000ul)
189/*
190 * Extract bits from address
191 */
192#define ADDR_SR_SHFT 28
193#define ADDR_PIDX 0x0ffff000UL
194#define ADDR_PIDX_SHFT 12
195#define ADDR_API_SHFT 22
196#define ADDR_API_SHFT64 16
197#define ADDR_POFF 0x00000fffUL
198
199/*
200 * Bits in DSISR:
201 */
202#define DSISR_DIRECT 0x80000000
203#define DSISR_NOTFOUND 0x40000000
204#define DSISR_PROTECT 0x08000000
205#define DSISR_INVRX 0x04000000
206#define DSISR_STORE 0x02000000
207#define DSISR_DABR 0x00400000
208#define DSISR_SEGMENT 0x00200000
209#define DSISR_EAR 0x00100000
210
211/*
212 * Bits in SRR1 on ISI:
213 */
214#define ISSRR1_NOTFOUND 0x40000000
215#define ISSRR1_DIRECT 0x10000000
216#define ISSRR1_PROTECT 0x08000000
217#define ISSRR1_SEGMENT 0x00200000
218
219#else /* BOOKE */
220
221#include <machine/tlb.h>
222
223/*
224 * Flags for pte_remove() routine.
225 */
226#define PTBL_HOLD 0x00000001 /* do not unhold ptbl pages */
227#define PTBL_UNHOLD 0x00000002 /* unhold and attempt to free ptbl pages */
228
229#define PTBL_HOLD_FLAG(pmap) (((pmap) == kernel_pmap) ? PTBL_HOLD : PTBL_UNHOLD)
230
231/*
232 * Page Table Entry definitions and macros.
233 *
234 * RPN need only be 32-bit because Book-E has 36-bit addresses, and the smallest
235 * page size is 4k (12-bit mask), so RPN can really fit into 24 bits.
236 */
237#ifndef LOCORE
238typedef uint64_t pte_t;
239#endif
240
241/* RPN mask, TLB0 4K pages */
242#define PTE_PA_MASK PAGE_MASK
243
244#if defined(BOOKE_E500)
245
246/* PTE bits assigned to MAS2, MAS3 flags */
247#define PTE_MAS2_SHIFT 19
248#define PTE_W (MAS2_W << PTE_MAS2_SHIFT)
249#define PTE_I (MAS2_I << PTE_MAS2_SHIFT)
250#define PTE_M (MAS2_M << PTE_MAS2_SHIFT)
251#define PTE_G (MAS2_G << PTE_MAS2_SHIFT)
252#define PTE_MAS2_MASK (MAS2_G | MAS2_M | MAS2_I | MAS2_W)
253
254#define PTE_MAS3_SHIFT 2
255#define PTE_UX (MAS3_UX << PTE_MAS3_SHIFT)
256#define PTE_SX (MAS3_SX << PTE_MAS3_SHIFT)
257#define PTE_UW (MAS3_UW << PTE_MAS3_SHIFT)
258#define PTE_SW (MAS3_SW << PTE_MAS3_SHIFT)
259#define PTE_UR (MAS3_UR << PTE_MAS3_SHIFT)
260#define PTE_SR (MAS3_SR << PTE_MAS3_SHIFT)
261#define PTE_MAS3_MASK ((MAS3_UX | MAS3_SX | MAS3_UW \
262 | MAS3_SW | MAS3_UR | MAS3_SR) << PTE_MAS3_SHIFT)
263
264#define PTE_PS_SHIFT 8
265#define PTE_PS_4KB (2 << PTE_PS_SHIFT)
266
267#endif
268
269/* Other PTE flags */
270#define PTE_VALID 0x00000001 /* Valid */
271#define PTE_MODIFIED 0x00001000 /* Modified */
272#define PTE_WIRED 0x00002000 /* Wired */
273#define PTE_MANAGED 0x00000002 /* Managed */
274#define PTE_REFERENCED 0x00040000 /* Referenced */
275
276/*
277 * Page Table Entry definitions and macros.
278 *
279 * We use the hardware page table entry format:
280 *
281 * 63 24 23 19 18 17 14 13 12 11 8 7 6 5 4 3 2 1 0
282 * ---------------------------------------------------------------
283 * ARPN(12:51) WIMGE R U0:U3 SW0 C PSIZE UX SX UW SW UR SR SW1 V
284 * ---------------------------------------------------------------
285 */
286
287/* PTE fields. */
288#define PTE_TSIZE_SHIFT (63-54)
289#define PTE_TSIZE_MASK 0x7
290#define PTE_TSIZE_SHIFT_DIRECT (63-55)
291#define PTE_TSIZE_MASK_DIRECT 0xf
292#define PTE_PS_DIRECT(ps) (ps<<PTE_TSIZE_SHIFT_DIRECT) /* Direct Entry Page Size */
293#define PTE_PS(ps) (ps<<PTE_TSIZE_SHIFT) /* Page Size */
294
295/* Macro argument must of pte_t type. */
296#define PTE_TSIZE(pte) (int)((*pte >> PTE_TSIZE_SHIFT) & PTE_TSIZE_MASK)
297#define PTE_TSIZE_DIRECT(pte) (int)((*pte >> PTE_TSIZE_SHIFT_DIRECT) & PTE_TSIZE_MASK_DIRECT)
298
299/* Macro argument must of pte_t type. */
300#define PTE_ARPN_SHIFT 12
301#define PTE_FLAGS_MASK 0x00ffffff
302#define PTE_RPN_FROM_PA(pa) (((pa) & ~PAGE_MASK) << PTE_ARPN_SHIFT)
303#define PTE_PA(pte) ((vm_paddr_t)(*pte >> PTE_ARPN_SHIFT) & ~PAGE_MASK)
304#define PTE_ISVALID(pte) ((*pte) & PTE_VALID)
305#define PTE_ISWIRED(pte) ((*pte) & PTE_WIRED)
306#define PTE_ISMANAGED(pte) ((*pte) & PTE_MANAGED)
307#define PTE_ISMODIFIED(pte) ((*pte) & PTE_MODIFIED)
308#define PTE_ISREFERENCED(pte) ((*pte) & PTE_REFERENCED)
309
310#endif /* BOOKE */
311
312/* Book-E page table format, broken out for the generic pmap.h. */
313#ifdef __powerpc64__
314
315#include <machine/tlb.h>
316
317/*
318 * The virtual address is:
319 *
320 * 4K page size
321 * +-----+-----------+-------+-------------+-------------+----------------+
322 * | - | pg_root |pdir_l1| dir# | pte# | off in 4K page |
323 * +-----+-----------+-------+-------------+-------------+----------------+
324 * 63 52 51 39 38 30 29 ^ 21 20 ^ 12 11 0
325 * | |
326 * index in 1 page of pointers
327 *
328 * 1st level - Root page table
329 *
330 * pp2d consists of PG_ROOT_NENTRIES entries, each being a pointer to
331 * second level entity, i.e. the page table directory (pdir).
332 */
333#define PG_ROOT_H 51
334#define PG_ROOT_L 39
335#define PG_ROOT_SIZE (1UL << PG_ROOT_L) /* va range mapped by pp2d */
336#define PG_ROOT_SHIFT PG_ROOT_L
337#define PG_ROOT_NUM (PG_ROOT_H - PG_ROOT_L + 1)
338#define PG_ROOT_MASK ((1 << PG_ROOT_NUM) - 1)
339#define PG_ROOT_IDX(va) ((va >> PG_ROOT_SHIFT) & PG_ROOT_MASK)
340#define PG_ROOT_NENTRIES (1 << PG_ROOT_NUM)
341#define PG_ROOT_ENTRY_SHIFT 3 /* log2 (sizeof(struct pte_entry **)) */
342
343/*
344 * 2nd level - page directory directory (pdir l1)
345 *
346 * pdir consists of PDIR_NENTRIES entries, each being a pointer to
347 * second level entity, i.e. the actual page table (ptbl).
348 */
349#define PDIR_L1_H (PG_ROOT_L-1)
350#define PDIR_L1_L 30
351#define PDIR_L1_NUM (PDIR_L1_H-PDIR_L1_L+1)
352#define PDIR_L1_SIZE (1 << PDIR_L1_L) /* va range mapped by pdir */
353#define PDIR_L1_MASK ((1<<PDIR_L1_NUM)-1)
354#define PDIR_L1_SHIFT PDIR_L1_L
355#define PDIR_L1_NENTRIES (1<<PDIR_L1_NUM)
356#define PDIR_L1_IDX(va) (((va) >> PDIR_L1_SHIFT) & PDIR_L1_MASK)
357#define PDIR_L1_ENTRY_SHIFT 3 /* log2 (sizeof(struct pte_entry *)) */
358#define PDIR_L1_PAGES ((PDIR_L1_NENTRIES * (1<<PDIR_L1_ENTRY_SHIFT)) / PAGE_SIZE)
359
360/*
361 * 3rd level - page table directory (pdir)
362 *
363 * pdir consists of PDIR_NENTRIES entries, each being a pointer to
364 * second level entity, i.e. the actual page table (ptbl).
365 */
366#define PDIR_H (PDIR_L1_L-1)
367#define PDIR_L 21
368#define PDIR_NUM (PDIR_H-PDIR_L+1)
369#define PDIR_SIZE (1 << PDIR_L) /* va range mapped by pdir */
370#define PDIR_MASK ((1<<PDIR_NUM)-1)
371#define PDIR_SHIFT PDIR_L
372#define PDIR_NENTRIES (1<<PDIR_NUM)
373#define PDIR_IDX(va) (((va) >> PDIR_SHIFT) & PDIR_MASK)
374#define PDIR_ENTRY_SHIFT 3 /* log2 (sizeof(struct pte_entry *)) */
375#define PDIR_PAGES ((PDIR_NENTRIES * (1<<PDIR_ENTRY_SHIFT)) / PAGE_SIZE)
376
377/*
378 * 4th level - page table (ptbl)
379 *
380 * Page table covers PTBL_NENTRIES page table entries. Page
381 * table entry (pte) is 64 bit wide and defines mapping
382 * for a single page.
383 */
384#define PTBL_H (PDIR_L-1)
385#define PTBL_L PAGE_SHIFT
386#define PTBL_NUM (PTBL_H-PTBL_L+1)
387#define PTBL_MASK ((1<<PTBL_NUM)-1)
388#define PTBL_SHIFT PTBL_L
389#define PTBL_SIZE PAGE_SIZE /* va range mapped by ptbl entry */
390#define PTBL_NENTRIES (1<<PTBL_NUM)
391#define PTBL_IDX(va) ((va >> PTBL_SHIFT) & PTBL_MASK)
392#define PTBL_ENTRY_SHIFT 3 /* log2 (sizeof (struct pte_entry)) */
393#define PTBL_PAGES ((PTBL_NENTRIES * (1<<PTBL_ENTRY_SHIFT)) / PAGE_SIZE)
394
395#else
396/*
397 * 1st level - page table directory (pdir)
398 *
399 * pdir consists of 1024 entries, each being a pointer to
400 * second level entity, i.e. the actual page table (ptbl).
401 */
402#define PDIR_SHIFT 22
403#define PDIR_SIZE (1 << PDIR_SHIFT) /* va range mapped by pdir */
404#define PDIR_MASK (~(PDIR_SIZE - 1))
405#define PDIR_NENTRIES 1024 /* number of page tables in pdir */
406
407/* Returns pdir entry number for given va */
408#define PDIR_IDX(va) ((va) >> PDIR_SHIFT)
409
410#define PDIR_ENTRY_SHIFT 2 /* entry size is 2^2 = 4 bytes */
411
412/*
413 * 2nd level - page table (ptbl)
414 *
415 * Page table covers 1024 page table entries. Page
416 * table entry (pte) is 32 bit wide and defines mapping
417 * for a single page.
418 */
419#define PTBL_SHIFT PAGE_SHIFT
420#define PTBL_SIZE PAGE_SIZE /* va range mapped by ptbl entry */
421#define PTBL_MASK ((PDIR_SIZE - 1) & ~((1 << PAGE_SHIFT) - 1))
422#define PTBL_NENTRIES 1024 /* number of pages mapped by ptbl */
423
424/* Returns ptbl entry number for given va */
425#define PTBL_IDX(va) (((va) & PTBL_MASK) >> PTBL_SHIFT)
426
427/* Size of ptbl in pages, 1024 entries, each sizeof(struct pte_entry). */
428#define PTBL_PAGES 2
429#define PTBL_ENTRY_SHIFT 3 /* entry size is 2^3 = 8 bytes */
430
431#endif
432#endif /* _MACHINE_PTE_H_ */