1/*-
2 * Copyright (c) 2015-2016 Ruslan Bukin <br@bsdpad.com>
3 * All rights reserved.
4 *
5 * Portions of this software were developed by SRI International and the
6 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
7 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
8 *
9 * Portions of this software were developed by the University of Cambridge
10 * Computer Laboratory as part of the CTSRD Project, with support from the
11 * UK Higher Education Innovation Fund (HEIF).
12 *
13 * Redistribution and use in source and binary forms, with or without
14 * modification, are permitted provided that the following conditions
15 * are met:
16 * 1. Redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer.
18 * 2. Redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 */
34
35#ifndef _MACHINE_CPUFUNC_H_
36#define _MACHINE_CPUFUNC_H_
37
38static __inline void
39breakpoint(void)
40{
41
42 __asm("ebreak");
43}
44
45#ifdef _KERNEL
46
47#include <sys/_null.h>
48
49#include <machine/riscvreg.h>
50
51static __inline register_t
52intr_disable(void)
53{
54 uint64_t ret;
55
56 __asm __volatile(
57 "csrrci %0, sstatus, %1"
58 : "=&r" (ret) : "i" (SSTATUS_SIE)
59 );
60
61 return (ret & (SSTATUS_SIE));
62}
63
64static __inline void
65intr_restore(register_t s)
66{
67
68 __asm __volatile(
69 "csrs sstatus, %0"
70 :: "r" (s)
71 );
72}
73
74static __inline void
75intr_enable(void)
76{
77
78 __asm __volatile(
79 "csrsi sstatus, %0"
80 :: "i" (SSTATUS_SIE)
81 );
82}
83
84/* NB: fence() is defined as a macro in <machine/atomic.h>. */
85
86static __inline void
87fence_i(void)
88{
89
90 __asm __volatile("fence.i" ::: "memory");
91}
92
93static __inline void
94sfence_vma(void)
95{
96
97 __asm __volatile("sfence.vma" ::: "memory");
98}
99
100static __inline void
101sfence_vma_page(uintptr_t addr)
102{
103
104 __asm __volatile("sfence.vma %0" :: "r" (addr) : "memory");
105}
106
107static __inline void
108sfence_vma_asid(uint64_t asid)
109{
110
111 __asm __volatile("sfence.vma x0, %0" :: "r" (asid) : "memory");
112}
113
114static __inline void
115sfence_vma_asid_page(uint64_t asid, uintptr_t addr)
116{
117
118 __asm __volatile("sfence.vma %0, %1" :: "r" (addr), "r" (asid)
119 : "memory");
120}
121
122#define rdcycle() csr_read64(cycle)
123#define rdtime() csr_read64(time)
124#define rdinstret() csr_read64(instret)
125#define rdhpmcounter(n) csr_read64(hpmcounter##n)
126
127/* Cache hooks. */
128
129extern int64_t dcache_line_size;
130
131typedef void (*cache_op_t)(vm_offset_t start, vm_size_t size);
132
133struct riscv_cache_ops {
134 cache_op_t dcache_wbinv_range;
135 cache_op_t dcache_inv_range;
136 cache_op_t dcache_wb_range;
137};
138
139extern struct riscv_cache_ops cache_ops;
140
141static __inline void
142cpu_dcache_wbinv_range(vm_offset_t addr, vm_size_t size)
143{
144 if (cache_ops.dcache_wbinv_range != NULL)
145 cache_ops.dcache_wbinv_range(addr, size);
146}
147
148static __inline void
149cpu_dcache_inv_range(vm_offset_t addr, vm_size_t size)
150{
151 if (cache_ops.dcache_inv_range != NULL)
152 cache_ops.dcache_inv_range(addr, size);
153}
154
155static __inline void
156cpu_dcache_wb_range(vm_offset_t addr, vm_size_t size)
157{
158 if (cache_ops.dcache_wb_range != NULL)
159 cache_ops.dcache_wb_range(addr, size);
160}
161
162void riscv_cache_install_hooks(struct riscv_cache_ops *, u_int);
163
164#define cpufunc_nullop() riscv_nullop()
165
166void riscv_nullop(void);
167
168#endif /* _KERNEL */
169#endif /* _MACHINE_CPUFUNC_H_ */