1/*-
2 * Copyright (c) 2014 Andrew Turner
3 * Copyright (c) 2015-2018 Ruslan Bukin <br@bsdpad.com>
4 * All rights reserved.
5 *
6 * Portions of this software were developed by SRI International and the
7 * University of Cambridge Computer Laboratory under DARPA/AFRL contract
8 * FA8750-10-C-0237 ("CTSRD"), as part of the DARPA CRASH research programme.
9 *
10 * Portions of this software were developed by the University of Cambridge
11 * Computer Laboratory as part of the CTSRD Project, with support from the
12 * UK Higher Education Innovation Fund (HEIF).
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
16 * are met:
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
27 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
28 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
29 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
30 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
31 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
32 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
33 * SUCH DAMAGE.
34 */
35
36#ifndef _MACHINE_PTE_H_
37#define _MACHINE_PTE_H_
38
39#ifndef LOCORE
40typedef uint64_t pd_entry_t; /* page directory entry */
41typedef uint64_t pt_entry_t; /* page table entry */
42typedef uint64_t pn_t; /* page number */
43#endif
44
45/* Level 0 table, 512GiB per entry, SV48 only */
46#define L0_SHIFT 39
47#define L0_SIZE (1UL << L0_SHIFT)
48#define L0_OFFSET (L0_SIZE - 1)
49
50/* Level 1 table, 1GiB per entry */
51#define L1_SHIFT 30
52#define L1_SIZE (1UL << L1_SHIFT)
53#define L1_OFFSET (L1_SIZE - 1)
54
55/* Level 2 table, 2MiB per entry */
56#define L2_SHIFT 21
57#define L2_SIZE (1UL << L2_SHIFT)
58#define L2_OFFSET (L2_SIZE - 1)
59
60/* Level 3 table, 4KiB per entry */
61#define L3_SHIFT 12
62#define L3_SIZE (1UL << L3_SHIFT)
63#define L3_OFFSET (L3_SIZE - 1)
64
65#define Ln_ENTRIES_SHIFT 9
66#define Ln_ENTRIES (1 << Ln_ENTRIES_SHIFT)
67#define Ln_ADDR_MASK (Ln_ENTRIES - 1)
68
69/* Bits 9:8 are reserved for software */
70#define PTE_SW_MANAGED (1 << 9)
71#define PTE_SW_WIRED (1 << 8)
72#define PTE_D (1 << 7) /* Dirty */
73#define PTE_A (1 << 6) /* Accessed */
74#define PTE_G (1 << 5) /* Global */
75#define PTE_U (1 << 4) /* User */
76#define PTE_X (1 << 3) /* Execute */
77#define PTE_W (1 << 2) /* Write */
78#define PTE_R (1 << 1) /* Read */
79#define PTE_V (1 << 0) /* Valid */
80#define PTE_RWX (PTE_R | PTE_W | PTE_X)
81#define PTE_RX (PTE_R | PTE_X)
82#define PTE_KERN (PTE_V | PTE_R | PTE_W | PTE_A | PTE_D)
83#define PTE_PROMOTE (PTE_V | PTE_RWX | PTE_D | PTE_G | PTE_U | \
84 PTE_SW_MANAGED | PTE_SW_WIRED)
85
86/*
87 * Svpbmt Memory Attribute (MA) bits [62:61].
88 *
89 * +------+-------+------------------------------------------------------------+
90 * | Mode | Value | Requested Memory Attributes |
91 * +------+-------+------------------------------------------------------------+
92 * | PMA | 00 | None, inherited from Physical Memory Attributes (firmware) |
93 * | NC | 01 | Non-cacheable, idempotent, weakly-ordered (RVWMO), |
94 * | | | main memory |
95 * | IO | 10 | Non-cacheable, non-idempotent, strongly-ordered, I/O |
96 * | -- | 11 | Reserved |
97 * +------+-------+------------------------------------------------------------+
98 */
99#define PTE_MA_SHIFT 61
100#define PTE_MA_MASK (0x3ul << PTE_MA_SHIFT)
101#define PTE_MA_NONE (0ul)
102#define PTE_MA_NC (1ul << PTE_MA_SHIFT)
103#define PTE_MA_IO (2ul << PTE_MA_SHIFT)
104
105/*
106 * T-HEAD Custom Memory Attribute (MA) bits [63:59].
107 *
108 * bit 59: Trustable (relating to TEE)
109 * bit 60: Shareable (among CPUs, not configurable)
110 * bit 61: Bufferable (writes to device memory)
111 * bit 62: Cacheable
112 * bit 63: Memory Ordering (1 = strongly ordered (device), 0 = default)
113 *
114 * +------+-------+------------------------------------------------------------+
115 * | Mode | Value | Requested Memory Attributes |
116 * +------+-------+------------------------------------------------------------+
117 * | NC | 00110 | Weakly-ordered, non-cacheable, bufferable, shareable, |
118 * | | | non-trustable |
119 * | PMA | 01110 | Weakly-ordered, cacheable, bufferable, shareable, |
120 * | | | non-trustable |
121 * | IO | 10010 | Strongly-ordered, non-cacheable, non-bufferable, |
122 * | | | shareable, non-trustable |
123 * +------+-------+------------------------------------------------------------+
124 */
125#define PTE_THEAD_MA_SHIFT 59
126#define PTE_THEAD_MA_MASK (0x1ful << PTE_THEAD_MA_SHIFT)
127#define PTE_THEAD_MA_NC (0x6ul << PTE_THEAD_MA_SHIFT)
128#define PTE_THEAD_MA_NONE (0xeul << PTE_THEAD_MA_SHIFT)
129#define PTE_THEAD_MA_IO (0x12ul << PTE_THEAD_MA_SHIFT)
130
131/* Bits 63 - 54 are reserved for future use. */
132#define PTE_HI_MASK 0xFFC0000000000000ULL
133
134#define PTE_PPN0_S 10
135#define PTE_PPN1_S 19
136#define PTE_PPN2_S 28
137#define PTE_PPN3_S 37
138#define PTE_SIZE 8
139
140#endif /* !_MACHINE_PTE_H_ */