1/* $OpenBSD: pte.h,v 1.5 2026/04/05 11:48:17 kettenis Exp $ */
2
3/*
4 * Copyright (c) 2019 Brian Bamsch <bbamsch@google.com>
5 * Copyright (c) 2014 Dale Rahn <drahn@dalerahn.com>
6 *
7 * Permission to use, copy, modify, and distribute this software for any
8 * purpose with or without fee is hereby granted, provided that the above
9 * copyright notice and this permission notice appear in all copies.
10 *
11 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
12 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
13 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
14 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
15 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
16 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
17 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
18 */
19#ifndef _RISCV64_PTE_H_
20#define _RISCV64_PTE_H_
21
22#define Lx_TABLE_ALIGN (4096)
23
24/* Block and Page attributes */
25/* Bits 9:8 are reserved for software */
26#define PTE_ATTR_MASK (0x3ffUL)
27#define PTE_SW_MANAGED (1 << 9)
28#define PTE_SW_WIRED (1 << 8)
29#define PTE_D (1 << 7) /* Dirty */
30#define PTE_A (1 << 6) /* Accessed */
31#define PTE_G (1 << 5) /* Global */
32#define PTE_U (1 << 4) /* User */
33#define PTE_X (1 << 3) /* Execute */
34#define PTE_W (1 << 2) /* Write */
35#define PTE_R (1 << 1) /* Read */
36#define PTE_V (1 << 0) /* Valid */
37#define PTE_RWX (PTE_R | PTE_W | PTE_X)
38#define PTE_RX (PTE_R | PTE_X)
39#define PTE_KERN (PTE_V | PTE_R | PTE_W | PTE_A | PTE_D)
40
41/* Svpmbt extension */
42#define PTE_PMA (0ULL << 61)
43#define PTE_NC (1ULL << 61)
44#define PTE_IO (2ULL << 61)
45
46/* Svnapot extension */
47#define PTE_N (1ULL << 63)
48
49/* T-Head extended page attributes */
50#define PTE_THEAD_SO (1ULL << 63)
51#define PTE_THEAD_C (1ULL << 62)
52#define PTE_THEAD_B (1ULL << 61)
53#define PTE_THEAD_SH (1ULL << 60)
54
55/* Level 0 table, 512GiB per entry */
56#define L0_SHIFT 39
57
58/* Level 1 table, 1GiB per entry */
59#define L1_SHIFT 30
60#define L1_SIZE (1UL << L1_SHIFT)
61#define L1_OFFSET (L1_SIZE - 1)
62
63/* Level 2 table, 2MiB per entry */
64#define L2_SHIFT 21
65#define L2_SIZE (1UL << L2_SHIFT)
66#define L2_OFFSET (L2_SIZE - 1)
67
68/* Level 3 table, 4KiB per entry */
69#define L3_SHIFT 12
70#define L3_SIZE (1UL << L3_SHIFT)
71#define L3_OFFSET (L3_SIZE - 1)
72
73/* page mapping */
74#define Ln_ENTRIES_SHIFT 9
75#define Ln_ENTRIES (1 << Ln_ENTRIES_SHIFT)
76#define Ln_ADDR_MASK (Ln_ENTRIES - 1)
77#define Ln_TABLE_MASK ((1 << 12) - 1)
78
79/* physical page number mask */
80#define PTE_RPGN (((1ULL << 56) - 1) & ~PAGE_MASK)
81
82#define PTE_PPN0_S 10
83#define PTE_PPN1_S 19
84#define PTE_PPN2_S 28
85#define PTE_PPN3_S 37
86#define PTE_SIZE 8
87
88#ifndef _LOCORE
89typedef uint64_t pt_entry_t; /* page table entry */
90typedef uint64_t pn_t; /* page number */
91#endif /* !_LOCORE */
92
93#endif /* _RISCV64_PTE_H_ */