1/* $NetBSD: pte.h,v 1.29 2025/01/07 18:51:05 andvar Exp $ */
2
3/*
4 * Copyright (c) 1996-1999 Eduardo Horvath
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 *
12 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
13 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
14 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
15 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE
16 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
17 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
18 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
19 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
20 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
21 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
22 * SUCH DAMAGE.
23 *
24 */
25
26#ifndef _MACHINE_PTE_H_
27#define _MACHINE_PTE_H_
28
29#if defined(_KERNEL_OPT)
30#include "opt_sparc_arch.h"
31#endif
32
33/*
34 * Address translation works as follows:
35 *
36 **
37 * For sun4u:
38 *
39 * Take your pick; it's all S/W anyway. We'll start by emulating a sun4.
40 * Oh, here's the sun4u TTE for reference:
41 *
42 * struct sun4u_tte {
43 * uint64 tag_g:1, (global flag)
44 * tag_reserved:2, (reserved for future use)
45 * tag_ctxt:13, (context for mapping)
46 * tag_unassigned:6,
47 * tag_va:42; (virtual address bits<64:22>)
48 * uint64 data_v:1, (valid bit)
49 * data_size:2, (page size [8K*8**<SIZE>])
50 * data_nfo:1, (no-fault only)
51 * data_ie:1, (invert endianness [inefficient])
52 * data_soft2:9, (reserved for S/W)
53 * data_reserved:7,(reserved for future use)
54 * data_pa:30, (physical address)
55 * data_soft:6, (reserved for S/W)
56 * data_lock:1, (lock into TLB)
57 * data_cacheable:2, (cacheability control)
58 * data_e:1, (explicit accesses only)
59 * data_priv:1, (privileged page)
60 * data_w:1, (writable)
61 * data_g:1; (same as tag_g)
62 * };
63 */
64
65/* virtual address to virtual page number */
66#define VA_SUN4_VPG(va) (((int)(va) >> 13) & 31)
67#define VA_SUN4C_VPG(va) (((int)(va) >> 12) & 63)
68#define VA_SUN4U_VPG(va) (((int)(va) >> 13) & 31)
69
70/* virtual address to offset within page */
71#define VA_SUN4_OFF(va) (((int)(va)) & 0x1FFF)
72#define VA_SUN4C_OFF(va) (((int)(va)) & 0xFFF)
73#define VA_SUN4U_OFF(va) (((int)(va)) & 0x1FFF)
74
75/* When we go to 64-bit VAs we need to handle the hole */
76#define VA_VPG(va) VA_SUN4U_VPG(va)
77#define VA_OFF(va) VA_SUN4U_OFF(va)
78
79#define PG_SHIFT4U 13
80#define MMU_PAGE_ALIGN 8192
81
82/* If you know where a tte is in the tsb, how do you find its va? */
83#define TSBVA(i) ((tsb[(i)].tag.f.tag_va<<22)|(((i)<<13)&0x3ff000))
84
85#ifndef _LOCORE
86/*
87 * This is the spitfire TTE.
88 *
89 * We could use bitmasks and shifts to construct this if
90 * we had a 64-bit compiler w/64-bit longs. Otherwise it's
91 * a real pain to do this in C.
92 */
93#if 0
94/* We don't use bitfields anyway. */
95struct sun4u_tag_fields {
96 uint64_t tag_g:1, /* global flag */
97 tag_reserved:2, /* reserved for future use */
98 tag_ctxt:13, /* context for mapping */
99 tag_unassigned:6,
100 tag_va:42; /* virtual address bits<64:22> */
101};
102union sun4u_tag { struct sun4u_tag_fields f; int64_t tag; };
103struct sun4u_data_fields {
104 uint64_t data_v:1, /* valid bit */
105 data_size:2, /* page size [8K*8**<SIZE>] */
106 data_nfo:1, /* no-fault only */
107 data_ie:1, /* invert endianness [inefficient] */
108 data_soft2:9, /* reserved for S/W */
109 data_reserved:7,/* reserved for future use */
110 data_pa:30, /* physical address */
111 data_tsblock:1, /* S/W TSB locked entry */
112 data_modified:1,/* S/W modified bit */
113 data_realw:1, /* S/W real writable bit (to manage modified) */
114 data_accessed:1,/* S/W accessed bit */
115 data_exec:1, /* S/W Executable */
116 data_onlyexec:1,/* S/W Executable only */
117 data_lock:1, /* lock into TLB */
118 data_cacheable:2, /* cacheability control */
119 data_e:1, /* explicit accesses only */
120 data_priv:1, /* privileged page */
121 data_w:1, /* writable */
122 data_g:1; /* same as tag_g */
123};
124union sun4u_data { struct sun4u_data_fields f; int64_t data; };
125struct sun4u_tte {
126 union sun4u_tag tag;
127 union sun4u_data data;
128};
129#else
130struct sun4u_tte {
131 int64_t tag;
132 int64_t data;
133};
134#endif
135typedef struct sun4u_tte pte_t;
136
137#endif /* _LOCORE */
138
139/* TSB tag masks */
140#define CTX_MASK ((1<<13)-1)
141#define TSB_TAG_CTX_SHIFT 48
142#define TSB_TAG_VA_SHIFT 22
143#define TSB_TAG_G 0x8000000000000000LL
144
145#define TSB_TAG_CTX(t) ((((int64_t)(t))>>TSB_TAG_CTX_SHIFT)&CTX_MASK)
146#define TSB_TAG_VA(t) ((((int64_t)(t))<<TSB_TAG_VA_SHIFT))
147#define TSB_TAG(g,ctx,va) ((((uint64_t)((g)!=0))<<63)|(((uint64_t)(ctx)&CTX_MASK)<<TSB_TAG_CTX_SHIFT)|(((uint64_t)va)>>TSB_TAG_VA_SHIFT))
148
149/* Page sizes */
150#define PGSZ_8K 0
151#define PGSZ_64K 1
152#define PGSZ_512K 2
153#define PGSZ_4M 3
154
155#define SUN4U_PGSZ_SHIFT 61
156#define SUN4U_TLB_SZ(s) (((uint64_t)(s))<<SUN4U_PGSZ_SHIFT)
157
158/* TLB data masks */
159#define SUN4U_TLB_V 0x8000000000000000LL
160#define SUN4U_TLB_8K SUN4U_TLB_SZ(PGSZ_8K)
161#define SUN4U_TLB_64K SUN4U_TLB_SZ(PGSZ_64K)
162#define SUN4U_TLB_512K SUN4U_TLB_SZ(PGSZ_512K)
163#define SUN4U_TLB_4M SUN4U_TLB_SZ(PGSZ_4M)
164#define SUN4U_TLB_SZ_MASK 0x6000000000000000LL
165#define SUN4U_TLB_NFO 0x1000000000000000LL
166#define SUN4U_TLB_IE 0x0800000000000000LL
167#define SUN4U_TLB_SOFT2_MASK 0x07fc000000000000LL
168#define SUN4U_TLB_RESERVED_MASK 0x0003f80000000000LL
169#define SUN4U_TLB_PA_MASK 0x000007ffffffe000LL
170#define SUN4U_TLB_SOFT_MASK 0x0000000000001f80LL
171/* S/W bits */
172/* Access & TSB locked bits are swapped so I can set access w/one insn */
173/* #define SUN4U_TLB_ACCESS 0x0000000000001000LL */
174#define SUN4U_TLB_ACCESS 0x0000000000000200LL
175#define SUN4U_TLB_MODIFY 0x0000000000000800LL
176#define SUN4U_TLB_REAL_W 0x0000000000000400LL
177/* #define SUN4U_TLB_TSB_LOCK 0x0000000000000200LL */
178#define SUN4U_TLB_TSB_LOCK 0x0000000000001000LL
179#define SUN4U_TLB_EXEC 0x0000000000000100LL
180#define SUN4U_TLB_EXEC_ONLY 0x0000000000000080LL
181/* H/W bits */
182#define SUN4U_TLB_L 0x0000000000000040LL
183#define SUN4U_TLB_CACHE_MASK 0x0000000000000030LL
184#define SUN4U_TLB_CP 0x0000000000000020LL
185#define SUN4U_TLB_CV 0x0000000000000010LL
186#define SUN4U_TLB_E 0x0000000000000008LL
187#define SUN4U_TLB_P 0x0000000000000004LL
188#define SUN4U_TLB_W 0x0000000000000002LL
189#define SUN4U_TLB_G 0x0000000000000001LL
190
191/* Use a bit in the SOFT2 area to indicate a locked mapping. */
192#define TLB_WIRED 0x0010000000000000LL
193
194/*
195 * The following bits are used by locore so they should
196 * be duplicates of the above w/o the "long long"
197 */
198/* S/W bits */
199/* #define SUN4U_TTE_ACCESS 0x0000000000001000 */
200#define SUN4U_TTE_ACCESS 0x0000000000000200
201#define SUN4U_TTE_MODIFY 0x0000000000000800
202#define SUN4U_TTE_REAL_W 0x0000000000000400
203/* #define SUN4U_TTE_TSB_LOCK 0x0000000000000200 */
204#define SUN4U_TTE_TSB_LOCK 0x0000000000001000
205#define SUN4U_TTE_EXEC 0x0000000000000100
206#define SUN4U_TTE_EXEC_ONLY 0x0000000000000080
207/* H/W bits */
208#define SUN4U_TTE_L 0x0000000000000040
209#define SUN4U_TTE_CACHE_MASK 0x0000000000000030
210#define SUN4U_TTE_CP 0x0000000000000020
211#define SUN4U_TTE_CV 0x0000000000000010
212#define SUN4U_TTE_E 0x0000000000000008
213#define SUN4U_TTE_P 0x0000000000000004
214#define SUN4U_TTE_W 0x0000000000000002
215#define SUN4U_TTE_G 0x0000000000000001
216
217#define TTE_DATA_BITS "\177\20" \
218 "b\77V\0" "f\75\2SIZE\0" "b\77V\0" "f\75\2SIZE\0" \
219 "=\0008K\0" "=\00164K\0" "=\002512K\0" "=\0034M\0" \
220 "b\74NFO\0" "b\73IE\0" "f\62\10SOFT2\0" \
221 "f\51\10DIAG\0" "f\15\33PA<40:13>\0" "f\7\5SOFT\0" \
222 "b\6L\0" "b\5CP\0" "b\4CV\0" \
223 "b\3E\0" "b\2P\0" "b\1W\0" "b\0G\0"
224
225#define SUN4V_PGSZ_SHIFT 0
226#define SUN4V_TLB_SZ(s) (((uint64_t)(s))<<SUN4V_PGSZ_SHIFT)
227
228/* TLB data masks */
229#define SUN4V_TLB_V 0x8000000000000000LL
230#define SUN4V_TLB_8K SUN4V_TLB_SZ(PGSZ_8K)
231#define SUN4V_TLB_64K SUN4V_TLB_SZ(PGSZ_64K)
232#define SUN4V_TLB_512K SUN4V_TLB_SZ(PGSZ_512K)
233#define SUN4V_TLB_4M SUN4V_TLB_SZ(PGSZ_4M)
234#define SUN4V_TLB_SZ_MASK 0x000000000000000fLL
235#define SUN4V_TLB_NFO 0x4000000000000000LL
236#define SUN4V_TLB_IE 0x0000000000001000LL
237#define SUN4V_TLB_SOFT2_MASK 0x3f00000000000000LL
238#define SUN4V_TLB_PA_MASK 0x00ffffffffffe000LL
239#define SUN4V_TLB_SOFT_MASK 0x0000000000000030LL
240/* S/W bits */
241#define SUN4V_TLB_ACCESS 0x0000000000000010LL
242#define SUN4V_TLB_MODIFY 0x0000000000000020LL
243#define SUN4V_TLB_REAL_W 0x2000000000000000LL
244#define SUN4V_TLB_TSB_LOCK 0x1000000000000000LL
245#define SUN4V_TLB_EXEC SUN4V_TLB_X
246#define SUN4V_TLB_EXEC_ONLY 0x0200000000000000LL
247/* H/W bits */
248#define SUN4V_TLB_CACHE_MASK 0x0000000000000600LL
249#define SUN4V_TLB_CP 0x0000000000000400LL
250#define SUN4V_TLB_CV 0x0000000000000200LL
251#define SUN4V_TLB_E 0x0000000000000800LL
252#define SUN4V_TLB_P 0x0000000000000100LL
253#define SUN4V_TLB_X 0x0000000000000080LL
254#define SUN4V_TLB_W 0x0000000000000040LL
255#define SUN4V_TLB_G 0x0000000000000000LL
256
257#define SUN4U_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie,wc) \
258(((valid)?SUN4U_TLB_V:0LL)|SUN4U_TLB_SZ(sz)|(((uint64_t)(pa))&SUN4U_TLB_PA_MASK)|\
259((cache)?((aliased)?SUN4U_TLB_CP:SUN4U_TLB_CACHE_MASK):((wc)?0LL:SUN4U_TLB_E))|\
260((priv)?SUN4U_TLB_P:0LL)|((write)?SUN4U_TLB_W:0LL)|((g)?SUN4U_TLB_G:0LL)|((ie)?SUN4U_TLB_IE:0LL))
261
262#define SUN4V_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie,wc) \
263(((valid)?SUN4V_TLB_V:0LL)|SUN4V_TLB_SZ(sz)|\
264(((u_int64_t)(pa))&SUN4V_TLB_PA_MASK)|\
265((cache)?((aliased)?SUN4V_TLB_CP:SUN4V_TLB_CACHE_MASK):((wc)?0LL:SUN4V_TLB_E))|\
266((priv)?SUN4V_TLB_P:0LL)|((write)?SUN4V_TLB_W:0LL)|((g)?SUN4V_TLB_G:0LL)|\
267((ie)?SUN4V_TLB_IE:0LL))
268
269#define TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie,wc) \
270(CPU_ISSUN4V ? SUN4V_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie,wc) : \
271 SUN4U_TSB_DATA(g,sz,pa,priv,write,cache,aliased,valid,ie,wc))
272
273#define TLB_EXEC (CPU_ISSUN4V ? SUN4V_TLB_EXEC : SUN4U_TLB_EXEC)
274#define TLB_V (CPU_ISSUN4V ? SUN4V_TLB_V : SUN4U_TLB_V)
275#define TLB_PA_MASK (CPU_ISSUN4V ? SUN4V_TLB_PA_MASK : SUN4U_TLB_PA_MASK)
276#define TLB_CP (CPU_ISSUN4V ? SUN4V_TLB_CP : SUN4U_TLB_CP)
277#define TLB_P (CPU_ISSUN4V ? SUN4V_TLB_P : SUN4U_TLB_P)
278#define TLB_W (CPU_ISSUN4V ? SUN4V_TLB_W : SUN4U_TLB_W)
279#define TLB_ACCESS (CPU_ISSUN4V ? SUN4V_TLB_ACCESS : SUN4U_TLB_ACCESS)
280#define TLB_MODIFY (CPU_ISSUN4V ? SUN4V_TLB_MODIFY : SUN4U_TLB_MODIFY)
281#define TLB_REAL_W (CPU_ISSUN4V ? SUN4V_TLB_REAL_W : SUN4U_TLB_REAL_W)
282#define TLB_TSB_LOCK (CPU_ISSUN4V ? SUN4V_TLB_TSB_LOCK : SUN4U_TLB_TSB_LOCK)
283#define TLB_EXEC_ONLY (CPU_ISSUN4V ? SUN4V_TLB_EXEC_ONLY : SUN4U_TLB_EXEC_ONLY)
284#define TLB_L (CPU_ISSUN4V ? 0 : SUN4U_TLB_L)
285#define TLB_CV (CPU_ISSUN4V ? SUN4V_TLB_CV : SUN4U_TLB_CV)
286#define TLB_IE (CPU_ISSUN4V ? SUN4V_TLB_IE : SUN4U_TLB_IE)
287
288#define MMU_CACHE_VIRT 0x3
289#define MMU_CACHE_PHYS 0x2
290#define MMU_CACHE_NONE 0x0
291
292/* This needs to be updated for sun4u IOMMUs */
293/*
294 * IOMMU PTE bits.
295 */
296#define IOPTE_PPN_MASK 0x07ffff00
297#define IOPTE_PPN_SHIFT 8
298#define IOPTE_RSVD 0x000000f1
299#define IOPTE_WRITE 0x00000004
300#define IOPTE_VALID 0x00000002
301
302/*
303 * This is purely for compatibility with the old SPARC machines.
304 */
305#define NBPRG (1 << 24) /* bytes per region */
306#define RGSHIFT 24 /* log2(NBPRG) */
307#define NSEGRG (NBPRG / NBPSG) /* segments per region */
308
309#define NBPSG (1 << 18) /* bytes per segment */
310#define SGSHIFT 18 /* log2(NBPSG) */
311
312/* there is no `struct pte'; we just use `int'; this is for non-4M only */
313#define PG_V 0x80000000
314#define PG_PFNUM 0x0007ffff /* n.b.: only 16 bits on sun4c */
315
316/* virtual address to virtual region number */
317#define VA_VREG(va) (((unsigned int)(va) >> RGSHIFT) & 255)
318
319/* virtual address to virtual segment number */
320#define VA_VSEG(va) (((unsigned int)(va) >> SGSHIFT) & 63)
321
322#ifndef _LOCORE
323typedef u_short pmeg_t; /* 10 bits needed per Sun-4 segmap entry */
324#endif
325
326/*
327 * Here are the bit definitions for 4M/SRMMU pte's
328 */
329 /* MMU TABLE ENTRIES */
330#define SRMMU_TETYPE 0x3 /* mask for table entry type */
331#define SRMMU_TEPTE 0x2 /* Page Table Entry */
332 /* PTE FIELDS */
333#define SRMMU_PPNMASK 0xFFFFFF00
334#define SRMMU_PPNPASHIFT 0x4 /* shift to put ppn into PAddr */
335
336#endif /* _MACHINE_PTE_H_ */