| 1 | /*	$OpenBSD: trap.h,v 1.5 2013/04/02 13:24:57 kettenis Exp $	*/ |
| 2 | /*	$NetBSD: trap.h,v 1.4 1999/06/07 05:28:04 eeh Exp $ */ |
| 3 | |
| 4 | /* |
| 5 | * Copyright (c) 1996-1999 Eduardo Horvath |
| 6 | * |
| 7 | * Redistribution and use in source and binary forms, with or without |
| 8 | * modification, are permitted provided that the following conditions |
| 9 | * are met: |
| 10 | * 1. Redistributions of source code must retain the above copyright |
| 11 | * notice, this list of conditions and the following disclaimer. |
| 12 | * |
| 13 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND |
| 14 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 15 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 16 | * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE |
| 17 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 18 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 19 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 20 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 21 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 22 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 23 | * SUCH DAMAGE. |
| 24 | * |
| 25 | */ |
| 26 | |
| 27 | |
| 28 | #ifndef	_MACHINE_TRAP_H |
| 29 | #define	_MACHINE_TRAP_H |
| 30 | |
| 31 | /*	trap		vec	 (pri) description	*/ |
| 32 | /*			0x000	 unused */ |
| 33 | #define	T_POR		0x001	/* (0) power on reset */ |
| 34 | #define T_WDR		0x002	/* (1) watchdog reset */ |
| 35 | #define T_XIR		0x003	/* (1) externally initiated reset */ |
| 36 | #define T_SIR		0x004	/* (1) software initiated reset */ |
| 37 | #define T_RED_EXCEPTION	0x005	/* (1) RED state exception */ |
| 38 | /*			0x006	 unused */ |
| 39 | /*			0x007	 unused */ |
| 40 | #define T_INST_EXCEPT	0x008	/* (5) instruction access exception */ |
| 41 | #define T_TEXTFAULT	0x009	/* (2) ? Text fault */ |
| 42 | #define T_INST_ERROR	0x00a	/* (3) instruction access error */ |
| 43 | /*			0x00b	 unused */ |
| 44 | /*	through		0x00f	 unused */ |
| 45 | #define T_ILLINST	0x010	/* (7) illegal instruction */ |
| 46 | #define T_PRIVINST	0x011	/* (6) privileged opcode */ |
| 47 | #define	T_UNIMP_LDD	0x012	/* (6) unimplemented LDD */ |
| 48 | #define	T_UNIMP_STD	0x013	/* (6) unimplemented STD */ |
| 49 | /*			0x014	 unused */ |
| 50 | /*	through		0x01f	 unused */ |
| 51 | #define T_FPDISABLED	0x020	/* (8) fpu disabled */ |
| 52 | #define T_FP_IEEE_754	0x021	/* (11) ieee 754 exception */ |
| 53 | #define T_FP_OTHER	0x022	/* (11) other fp exception */ |
| 54 | #define T_TAGOF		0x023	/* (14) tag overflow */ |
| 55 | #define T_CLEAN_WINDOW	0x024	/* (10) clean window exception */ |
| 56 | /*			0x025	 unused */ |
| 57 | /*	through		0x027	 unused */ |
| 58 | #define T_DIV0		0x028	/* (15) division routine was handed 0 */ |
| 59 | #define	T_PROCERR	0x029	/* (4) internal processor error */ |
| 60 | /*			0x02a	 unused */ |
| 61 | /*	through		0x02f	 unused */ |
| 62 | #define	T_DATAFAULT	0x030	/* (12) address fault during data fetch */ |
| 63 | #define	T_DATA_MMU_MISS	0x031	/* (12) data access MMU miss */ |
| 64 | #define T_DATA_ERROR	0x032	/* (12) data access error */ |
| 65 | #define T_DATA_PROT	0x033	/* (12) Data protection ??? */ |
| 66 | #define	T_ALIGN		0x034	/* (10) address not properly aligned */ |
| 67 | #define	T_LDDF_ALIGN	0x035	/* (10) LDDF address not properly aligned */ |
| 68 | #define	T_STDF_ALIGN	0x036	/* (10) STDF address not properly aligned */ |
| 69 | #define T_PRIVACT	0x037	/* (11) privileged action */ |
| 70 | #define	T_LDQF_ALIGN	0x038	/* (10) LDQF address not properly aligned */ |
| 71 | #define	T_STQF_ALIGN	0x039	/* (10) STQF address not properly aligned */ |
| 72 | /*			0x03a	 unused */ |
| 73 | /*	through		0x03f	 unused */ |
| 74 | #define T_ASYNC_ERROR	0x040	/* (2) ???? */ |
| 75 | #define	T_L1INT		0x041	/* (31) level 1 interrupt */ |
| 76 | #define	T_L2INT		0x042	/* (30) level 2 interrupt */ |
| 77 | #define	T_L3INT		0x043	/* (29) level 3 interrupt */ |
| 78 | #define	T_L4INT		0x044	/* (28) level 4 interrupt */ |
| 79 | #define	T_L5INT		0x045	/* (27) level 5 interrupt */ |
| 80 | #define	T_L6INT		0x046	/* (26) level 6 interrupt */ |
| 81 | #define	T_L7INT		0x047	/* (25) level 7 interrupt */ |
| 82 | #define	T_L8INT		0x048	/* (24) level 8 interrupt */ |
| 83 | #define	T_L9INT		0x049	/* (23) level 9 interrupt */ |
| 84 | #define	T_L10INT	0x04a	/* (22) level 10 interrupt */ |
| 85 | #define	T_L11INT	0x04b	/* (21) level 11 interrupt */ |
| 86 | #define	T_L12INT	0x04c	/* (20) level 12 interrupt */ |
| 87 | #define	T_L13INT	0x04d	/* (19) level 13 interrupt */ |
| 88 | #define	T_L14INT	0x04e	/* (18) level 14 interrupt */ |
| 89 | #define	T_L15INT	0x04f	/* (17) level 15 interrupt */ |
| 90 | /*			0x050	 unused */ |
| 91 | /*	through		0x05f	 unused */ |
| 92 | #define T_INTVEC	0x060	/* (16) interrupt vector [Interrupt Global Regs]*/ |
| 93 | #define T_PA_WATCHPT	0x061	/* (12) Physical addr data watchpoint */ |
| 94 | #define T_VA_WATCHPT	0x062	/* (11) Virtual addr data watchpoint */ |
| 95 | #define T_ECCERR	0x063	/* (33) ECC correction error */ |
| 96 | #define T_FIMMU_MISS	0x064	/* (2) fast instruction access MMU miss */ |
| 97 | /*	through		0x067	 unused */ |
| 98 | #define T_FDMMU_MISS	0x068	/* (2) fast data access MMU miss */ |
| 99 | /*	through		0x06b	 unused */ |
| 100 | #define T_FDMMU_PROT	0x06c	/* (2) fast data access protection */ |
| 101 | /*	through		0x06f	 unused */ |
| 102 | /* 0x070...0x07f implementation dependent exceptions */ |
| 103 | #define T_SPILL_N_NORM	0x080	/* (9) spill (n=0..7) normal */ |
| 104 | /*	through		0x09f	 unused */ |
| 105 | #define T_SPILL_N_OTHER	0x0a0	/* (9) spill (n=0..7) other */ |
| 106 | /*	through		0x0bf	 unused */ |
| 107 | #define T_FILL_N_NORM	0x0c0	/* (9) fill (n=0..7) normal */ |
| 108 | /*	through		0x0df	 unused */ |
| 109 | #define T_FILL_N_OTHER	0x0e0	/* (9) fill (n=0..7) other */ |
| 110 | /*	through		0x0ff	 unused */ |
| 111 | |
| 112 | /* beginning of `user' vectors (from trap instructions) - all priority 16 */ |
| 113 | #define	T_SUN_SYSCALL	0x100	/* system call */ |
| 114 | #define	T_BREAKPOINT	0x101	/* breakpoint `instruction' */ |
| 115 | #define	T_UDIV0		0x102	/* division routine was handed 0 */ |
| 116 | #define	T_FLUSHWIN	0x103	/* flush windows */ |
| 117 | #define	T_CLEANWIN	0x104	/* provide clean windows */ |
| 118 | #define	T_RANGECHECK	0x105	/* ? */ |
| 119 | #define	T_FIXALIGN	0x106	/* fix up unaligned accesses */ |
| 120 | #define	T_INTOF		0x107	/* integer overflow ? */ |
| 121 | #define	T_SVR4_SYSCALL	0x108	/* SVR4 system call */ |
| 122 | #define	T_BSD_SYSCALL	0x109	/* BSD system call */ |
| 123 | #define	T_KGDB_EXEC	0x10a	/* for kernel gdb */ |
| 124 | |
| 125 | /* 0x10b..0x1ff are currently unallocated, except the following */ |
| 126 | #define T_SVR4_GETCC		0x120 |
| 127 | #define T_SVR4_SETCC		0x121 |
| 128 | #define T_SVR4_GETPSR		0x122 |
| 129 | #define T_SVR4_SETPSR		0x123 |
| 130 | #define T_SVR4_GETHRTIME	0x124 |
| 131 | #define T_SVR4_GETHRVTIME	0x125 |
| 132 | #define T_SVR4_GETHRESTIME	0x127 |
| 133 | #define T_GETCC			0x132 |
| 134 | #define T_SETCC			0x133 |
| 135 | #define T_SVID_SYSCALL		0x164 |
| 136 | #define	T_SPARC_INTL_SYSCALL	0x165 |
| 137 | #define	T_OS_VENDOR_SYSCALL	0x166 |
| 138 | #define	T_HW_OEM_SYSCALL	0x167 |
| 139 | #define T_RTF_DEF_TRAP		0x168 |
| 140 | #define T_MON_BREAKPOINT	0x17f |
| 141 | |
| 142 | #ifdef _KERNEL			/* pseudo traps for locore.s */ |
| 143 | #define	T_RWRET		-1	/* need first user window for trap return */ |
| 144 | #define	T_AST		-2	/* no-op, just needed reschedule or profile */ |
| 145 | #endif |
| 146 | |
| 147 | /* flags to system call (flags in %g1 along with syscall number) */ |
| 148 | #define	SYSCALL_G2RFLAG	0x400	/* on success, return to %g2 rather than npc */ |
| 149 | |
| 150 | /* |
| 151 | * `software trap' macros to keep people happy (sparc v8 manual says not |
| 152 | * to set the upper bits). |
| 153 | */ |
| 154 | #define	ST_BREAKPOINT	(T_BREAKPOINT & 0x7f) |
| 155 | #define	ST_DIV0		(T_DIV0 & 0x7f) |
| 156 | #define	ST_FLUSHWIN	(T_FLUSHWIN & 0x7f) |
| 157 | #define	ST_SYSCALL	(T_SUN_SYSCALL & 0x7f) |
| 158 | |
| 159 | #endif /* _MACHINE_TRAP_H_ */ |