1/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
2
3#ifndef _ASM_X86_AMD_HSMP_H_
4#define _ASM_X86_AMD_HSMP_H_
5
6#include <linux/types.h>
7
8#pragma pack(4)
9
10#define HSMP_MAX_MSG_LEN 8
11
12/*
13 * HSMP Messages supported
14 */
15enum hsmp_message_ids {
16 HSMP_TEST = 1, /* 01h Increments input value by 1 */
17 HSMP_GET_SMU_VER, /* 02h SMU FW version */
18 HSMP_GET_PROTO_VER, /* 03h HSMP interface version */
19 HSMP_GET_SOCKET_POWER, /* 04h average package power consumption */
20 HSMP_SET_SOCKET_POWER_LIMIT, /* 05h Set the socket power limit */
21 HSMP_GET_SOCKET_POWER_LIMIT, /* 06h Get current socket power limit */
22 HSMP_GET_SOCKET_POWER_LIMIT_MAX,/* 07h Get maximum socket power value */
23 HSMP_SET_BOOST_LIMIT, /* 08h Set a core maximum frequency limit */
24 HSMP_SET_BOOST_LIMIT_SOCKET, /* 09h Set socket maximum frequency level */
25 HSMP_GET_BOOST_LIMIT, /* 0Ah Get current frequency limit */
26 HSMP_GET_PROC_HOT, /* 0Bh Get PROCHOT status */
27 HSMP_SET_XGMI_LINK_WIDTH, /* 0Ch Set max and min width of xGMI Link */
28 HSMP_SET_DF_PSTATE, /* 0Dh Alter APEnable/Disable messages behavior */
29 HSMP_SET_AUTO_DF_PSTATE, /* 0Eh Enable DF P-State Performance Boost algorithm */
30 HSMP_GET_FCLK_MCLK, /* 0Fh Get FCLK and MEMCLK for current socket */
31 HSMP_GET_CCLK_THROTTLE_LIMIT, /* 10h Get CCLK frequency limit in socket */
32 HSMP_GET_C0_PERCENT, /* 11h Get average C0 residency in socket */
33 HSMP_SET_NBIO_DPM_LEVEL, /* 12h Set max/min LCLK DPM Level for a given NBIO */
34 HSMP_GET_NBIO_DPM_LEVEL, /* 13h Get LCLK DPM level min and max for a given NBIO */
35 HSMP_GET_DDR_BANDWIDTH, /* 14h Get theoretical maximum and current DDR Bandwidth */
36 HSMP_GET_TEMP_MONITOR, /* 15h Get socket temperature */
37 HSMP_GET_DIMM_TEMP_RANGE, /* 16h Get per-DIMM temperature range and refresh rate */
38 HSMP_GET_DIMM_POWER, /* 17h Get per-DIMM power consumption */
39 HSMP_GET_DIMM_THERMAL, /* 18h Get per-DIMM thermal sensors */
40 HSMP_GET_SOCKET_FREQ_LIMIT, /* 19h Get current active frequency per socket */
41 HSMP_GET_CCLK_CORE_LIMIT, /* 1Ah Get CCLK frequency limit per core */
42 HSMP_GET_RAILS_SVI, /* 1Bh Get SVI-based Telemetry for all rails */
43 HSMP_GET_SOCKET_FMAX_FMIN, /* 1Ch Get Fmax and Fmin per socket */
44 HSMP_GET_IOLINK_BANDWITH, /* 1Dh Get current bandwidth on IO Link */
45 HSMP_GET_XGMI_BANDWITH, /* 1Eh Get current bandwidth on xGMI Link */
46 HSMP_SET_GMI3_WIDTH, /* 1Fh Set max and min GMI3 Link width */
47 HSMP_SET_PCI_RATE, /* 20h Control link rate on PCIe devices */
48 HSMP_SET_POWER_MODE, /* 21h Select power efficiency profile policy */
49 HSMP_SET_PSTATE_MAX_MIN, /* 22h Set the max and min DF P-State */
50 HSMP_GET_METRIC_TABLE_VER, /* 23h Get metrics table version */
51 HSMP_GET_METRIC_TABLE, /* 24h Get metrics table */
52 HSMP_GET_METRIC_TABLE_DRAM_ADDR,/* 25h Get metrics table dram address */
53 HSMP_SET_XGMI_PSTATE_RANGE, /* 26h Set xGMI P-state range */
54 HSMP_CPU_RAIL_ISO_FREQ_POLICY, /* 27h Get/Set Cpu Iso frequency policy */
55 HSMP_DFC_ENABLE_CTRL, /* 28h Enable/Disable DF C-state */
56 HSMP_GET_RAPL_UNITS = 0x30, /* 30h Get scaling factor for energy */
57 HSMP_GET_RAPL_CORE_COUNTER, /* 31h Get core energy counter value */
58 HSMP_GET_RAPL_PACKAGE_COUNTER, /* 32h Get package energy counter value */
59 HSMP_MSG_ID_MAX,
60};
61
62struct hsmp_message {
63 __u32 msg_id; /* Message ID */
64 __u16 num_args; /* Number of input argument words in message */
65 __u16 response_sz; /* Number of expected output/response words */
66 __u32 args[HSMP_MAX_MSG_LEN]; /* argument/response buffer */
67 __u16 sock_ind; /* socket number */
68};
69
70enum hsmp_msg_type {
71 HSMP_RSVD = -1,
72 HSMP_SET = 0,
73 HSMP_GET = 1,
74 HSMP_SET_GET = 2,
75};
76
77enum hsmp_proto_versions {
78 HSMP_PROTO_VER2 = 2,
79 HSMP_PROTO_VER3,
80 HSMP_PROTO_VER4,
81 HSMP_PROTO_VER5,
82 HSMP_PROTO_VER6,
83 HSMP_PROTO_VER7
84};
85
86struct hsmp_msg_desc {
87 int num_args;
88 int response_sz;
89 enum hsmp_msg_type type;
90};
91
92/*
93 * User may use these comments as reference, please find the
94 * supported list of messages and message definition in the
95 * HSMP chapter of respective family/model PPR.
96 *
97 * Not supported messages would return -ENOMSG.
98 */
99static const struct hsmp_msg_desc hsmp_msg_desc_table[]
100 __attribute__((unused)) = {
101 /* RESERVED */
102 {0, 0, HSMP_RSVD},
103
104 /*
105 * HSMP_TEST, num_args = 1, response_sz = 1
106 * input: args[0] = xx
107 * output: args[0] = xx + 1
108 */
109 {1, 1, HSMP_GET},
110
111 /*
112 * HSMP_GET_SMU_VER, num_args = 0, response_sz = 1
113 * output: args[0] = smu fw ver
114 */
115 {0, 1, HSMP_GET},
116
117 /*
118 * HSMP_GET_PROTO_VER, num_args = 0, response_sz = 1
119 * output: args[0] = proto version
120 */
121 {0, 1, HSMP_GET},
122
123 /*
124 * HSMP_GET_SOCKET_POWER, num_args = 0, response_sz = 1
125 * output: args[0] = socket power in mWatts
126 */
127 {0, 1, HSMP_GET},
128
129 /*
130 * HSMP_SET_SOCKET_POWER_LIMIT, num_args = 1, response_sz = 0
131 * input: args[0] = power limit value in mWatts
132 */
133 {1, 0, HSMP_SET},
134
135 /*
136 * HSMP_GET_SOCKET_POWER_LIMIT, num_args = 0, response_sz = 1
137 * output: args[0] = socket power limit value in mWatts
138 */
139 {0, 1, HSMP_GET},
140
141 /*
142 * HSMP_GET_SOCKET_POWER_LIMIT_MAX, num_args = 0, response_sz = 1
143 * output: args[0] = maximuam socket power limit in mWatts
144 */
145 {0, 1, HSMP_GET},
146
147 /*
148 * HSMP_SET_BOOST_LIMIT, num_args = 1, response_sz = 0
149 * input: args[0] = apic id[31:16] + boost limit value in MHz[15:0]
150 */
151 {1, 0, HSMP_SET},
152
153 /*
154 * HSMP_SET_BOOST_LIMIT_SOCKET, num_args = 1, response_sz = 0
155 * input: args[0] = boost limit value in MHz
156 */
157 {1, 0, HSMP_SET},
158
159 /*
160 * HSMP_GET_BOOST_LIMIT, num_args = 1, response_sz = 1
161 * input: args[0] = apic id
162 * output: args[0] = boost limit value in MHz
163 */
164 {1, 1, HSMP_GET},
165
166 /*
167 * HSMP_GET_PROC_HOT, num_args = 0, response_sz = 1
168 * output: args[0] = proc hot status
169 */
170 {0, 1, HSMP_GET},
171
172 /*
173 * HSMP_SET_XGMI_LINK_WIDTH, num_args = 1, response_sz = 0
174 * input: args[0] = min link width[15:8] + max link width[7:0]
175 */
176 {1, 0, HSMP_SET},
177
178 /*
179 * HSMP_SET_DF_PSTATE, num_args = 1, response_sz = 0
180 * input: args[0] = df pstate[7:0]
181 */
182 {1, 0, HSMP_SET},
183
184 /* HSMP_SET_AUTO_DF_PSTATE, num_args = 0, response_sz = 0 */
185 {0, 0, HSMP_SET},
186
187 /*
188 * HSMP_GET_FCLK_MCLK, num_args = 0, response_sz = 2
189 * output: args[0] = fclk in MHz, args[1] = mclk in MHz
190 */
191 {0, 2, HSMP_GET},
192
193 /*
194 * HSMP_GET_CCLK_THROTTLE_LIMIT, num_args = 0, response_sz = 1
195 * output: args[0] = core clock in MHz
196 */
197 {0, 1, HSMP_GET},
198
199 /*
200 * HSMP_GET_C0_PERCENT, num_args = 0, response_sz = 1
201 * output: args[0] = average c0 residency
202 */
203 {0, 1, HSMP_GET},
204
205 /*
206 * HSMP_SET_NBIO_DPM_LEVEL, num_args = 1, response_sz = 0
207 * input: args[0] = nbioid[23:16] + max dpm level[15:8] + min dpm level[7:0]
208 */
209 {1, 0, HSMP_SET},
210
211 /*
212 * HSMP_GET_NBIO_DPM_LEVEL, num_args = 1, response_sz = 1
213 * input: args[0] = nbioid[23:16]
214 * output: args[0] = max dpm level[15:8] + min dpm level[7:0]
215 */
216 {1, 1, HSMP_GET},
217
218 /*
219 * HSMP_GET_DDR_BANDWIDTH, num_args = 0, response_sz = 1
220 * output: args[0] = max bw in Gbps[31:20] + utilised bw in Gbps[19:8] +
221 * bw in percentage[7:0]
222 */
223 {0, 1, HSMP_GET},
224
225 /*
226 * HSMP_GET_TEMP_MONITOR, num_args = 0, response_sz = 1
227 * output: args[0] = temperature in degree celsius. [15:8] integer part +
228 * [7:5] fractional part
229 */
230 {0, 1, HSMP_GET},
231
232 /*
233 * HSMP_GET_DIMM_TEMP_RANGE, num_args = 1, response_sz = 1
234 * input: args[0] = DIMM address[7:0]
235 * output: args[0] = refresh rate[3] + temperature range[2:0]
236 */
237 {1, 1, HSMP_GET},
238
239 /*
240 * HSMP_GET_DIMM_POWER, num_args = 1, response_sz = 1
241 * input: args[0] = DIMM address[7:0]
242 * output: args[0] = DIMM power in mW[31:17] + update rate in ms[16:8] +
243 * DIMM address[7:0]
244 */
245 {1, 1, HSMP_GET},
246
247 /*
248 * HSMP_GET_DIMM_THERMAL, num_args = 1, response_sz = 1
249 * input: args[0] = DIMM address[7:0]
250 * output: args[0] = temperature in degree celsius[31:21] + update rate in ms[16:8] +
251 * DIMM address[7:0]
252 */
253 {1, 1, HSMP_GET},
254
255 /*
256 * HSMP_GET_SOCKET_FREQ_LIMIT, num_args = 0, response_sz = 1
257 * output: args[0] = frequency in MHz[31:16] + frequency source[15:0]
258 */
259 {0, 1, HSMP_GET},
260
261 /*
262 * HSMP_GET_CCLK_CORE_LIMIT, num_args = 1, response_sz = 1
263 * input: args[0] = apic id [31:0]
264 * output: args[0] = frequency in MHz[31:0]
265 */
266 {1, 1, HSMP_GET},
267
268 /*
269 * HSMP_GET_RAILS_SVI, num_args = 0, response_sz = 1
270 * output: args[0] = power in mW[31:0]
271 */
272 {0, 1, HSMP_GET},
273
274 /*
275 * HSMP_GET_SOCKET_FMAX_FMIN, num_args = 0, response_sz = 1
276 * output: args[0] = fmax in MHz[31:16] + fmin in MHz[15:0]
277 */
278 {0, 1, HSMP_GET},
279
280 /*
281 * HSMP_GET_IOLINK_BANDWITH, num_args = 1, response_sz = 1
282 * input: args[0] = link id[15:8] + bw type[2:0]
283 * output: args[0] = io bandwidth in Mbps[31:0]
284 */
285 {1, 1, HSMP_GET},
286
287 /*
288 * HSMP_GET_XGMI_BANDWITH, num_args = 1, response_sz = 1
289 * input: args[0] = link id[15:8] + bw type[2:0]
290 * output: args[0] = xgmi bandwidth in Mbps[31:0]
291 */
292 {1, 1, HSMP_GET},
293
294 /*
295 * HSMP_SET_GMI3_WIDTH, num_args = 1, response_sz = 0
296 * input: args[0] = min link width[15:8] + max link width[7:0]
297 */
298 {1, 0, HSMP_SET},
299
300 /*
301 * HSMP_SET_PCI_RATE, num_args = 1, response_sz = 1
302 * input: args[0] = link rate control value
303 * output: args[0] = previous link rate control value
304 */
305 {1, 1, HSMP_SET},
306
307 /*
308 * HSMP_SET_POWER_MODE, num_args = 1, response_sz = 0
309 * input: args[0] = power efficiency mode[2:0]
310 */
311 {1, 1, HSMP_SET_GET},
312
313 /*
314 * HSMP_SET_PSTATE_MAX_MIN, num_args = 1, response_sz = 0
315 * input: args[0] = min df pstate[15:8] + max df pstate[7:0]
316 */
317 {1, 0, HSMP_SET},
318
319 /*
320 * HSMP_GET_METRIC_TABLE_VER, num_args = 0, response_sz = 1
321 * output: args[0] = metrics table version
322 */
323 {0, 1, HSMP_GET},
324
325 /*
326 * HSMP_GET_METRIC_TABLE, num_args = 0, response_sz = 0
327 */
328 {0, 0, HSMP_GET},
329
330 /*
331 * HSMP_GET_METRIC_TABLE_DRAM_ADDR, num_args = 0, response_sz = 2
332 * output: args[0] = lower 32 bits of the address
333 * output: args[1] = upper 32 bits of the address
334 */
335 {0, 2, HSMP_GET},
336
337 /*
338 * HSMP_SET_XGMI_PSTATE_RANGE, num_args = 1, response_sz = 0
339 * input: args[0] = min xGMI p-state[15:8] + max xGMI p-state[7:0]
340 */
341 {1, 0, HSMP_SET},
342
343 /*
344 * HSMP_CPU_RAIL_ISO_FREQ_POLICY, num_args = 1, response_sz = 1
345 * input: args[0] = set/get policy[31] +
346 * disable/enable independent control[0]
347 * output: args[0] = current policy[0]
348 */
349 {1, 1, HSMP_SET_GET},
350
351 /*
352 * HSMP_DFC_ENABLE_CTRL, num_args = 1, response_sz = 1
353 * input: args[0] = set/get policy[31] + enable/disable DFC[0]
354 * output: args[0] = current policy[0]
355 */
356 {1, 1, HSMP_SET_GET},
357
358 /* RESERVED(0x29-0x2f) */
359 {0, 0, HSMP_RSVD},
360 {0, 0, HSMP_RSVD},
361 {0, 0, HSMP_RSVD},
362 {0, 0, HSMP_RSVD},
363 {0, 0, HSMP_RSVD},
364 {0, 0, HSMP_RSVD},
365 {0, 0, HSMP_RSVD},
366
367 /*
368 * HSMP_GET_RAPL_UNITS, response_sz = 1
369 * output: args[0] = tu value[19:16] + esu value[12:8]
370 */
371 {0, 1, HSMP_GET},
372
373 /*
374 * HSMP_GET_RAPL_CORE_COUNTER, num_args = 1, response_sz = 1
375 * input: args[0] = apic id[15:0]
376 * output: args[0] = lower 32 bits of energy
377 * output: args[1] = upper 32 bits of energy
378 */
379 {1, 2, HSMP_GET},
380
381 /*
382 * HSMP_GET_RAPL_PACKAGE_COUNTER, num_args = 0, response_sz = 1
383 * output: args[0] = lower 32 bits of energy
384 * output: args[1] = upper 32 bits of energy
385 */
386 {0, 2, HSMP_GET},
387
388};
389
390/* Metrics table (supported only with proto version 6) */
391struct hsmp_metric_table {
392 __u32 accumulation_counter;
393
394 /* TEMPERATURE */
395 __u32 max_socket_temperature;
396 __u32 max_vr_temperature;
397 __u32 max_hbm_temperature;
398 __u64 max_socket_temperature_acc;
399 __u64 max_vr_temperature_acc;
400 __u64 max_hbm_temperature_acc;
401
402 /* POWER */
403 __u32 socket_power_limit;
404 __u32 max_socket_power_limit;
405 __u32 socket_power;
406
407 /* ENERGY */
408 __u64 timestamp;
409 __u64 socket_energy_acc;
410 __u64 ccd_energy_acc;
411 __u64 xcd_energy_acc;
412 __u64 aid_energy_acc;
413 __u64 hbm_energy_acc;
414
415 /* FREQUENCY */
416 __u32 cclk_frequency_limit;
417 __u32 gfxclk_frequency_limit;
418 __u32 fclk_frequency;
419 __u32 uclk_frequency;
420 __u32 socclk_frequency[4];
421 __u32 vclk_frequency[4];
422 __u32 dclk_frequency[4];
423 __u32 lclk_frequency[4];
424 __u64 gfxclk_frequency_acc[8];
425 __u64 cclk_frequency_acc[96];
426
427 /* FREQUENCY RANGE */
428 __u32 max_cclk_frequency;
429 __u32 min_cclk_frequency;
430 __u32 max_gfxclk_frequency;
431 __u32 min_gfxclk_frequency;
432 __u32 fclk_frequency_table[4];
433 __u32 uclk_frequency_table[4];
434 __u32 socclk_frequency_table[4];
435 __u32 vclk_frequency_table[4];
436 __u32 dclk_frequency_table[4];
437 __u32 lclk_frequency_table[4];
438 __u32 max_lclk_dpm_range;
439 __u32 min_lclk_dpm_range;
440
441 /* XGMI */
442 __u32 xgmi_width;
443 __u32 xgmi_bitrate;
444 __u64 xgmi_read_bandwidth_acc[8];
445 __u64 xgmi_write_bandwidth_acc[8];
446
447 /* ACTIVITY */
448 __u32 socket_c0_residency;
449 __u32 socket_gfx_busy;
450 __u32 dram_bandwidth_utilization;
451 __u64 socket_c0_residency_acc;
452 __u64 socket_gfx_busy_acc;
453 __u64 dram_bandwidth_acc;
454 __u32 max_dram_bandwidth;
455 __u64 dram_bandwidth_utilization_acc;
456 __u64 pcie_bandwidth_acc[4];
457
458 /* THROTTLERS */
459 __u32 prochot_residency_acc;
460 __u32 ppt_residency_acc;
461 __u32 socket_thm_residency_acc;
462 __u32 vr_thm_residency_acc;
463 __u32 hbm_thm_residency_acc;
464 __u32 spare;
465
466 /* New items at the end to maintain driver compatibility */
467 __u32 gfxclk_frequency[8];
468};
469
470/* Reset to default packing */
471#pragma pack()
472
473/* Define unique ioctl command for hsmp msgs using generic _IOWR */
474#define HSMP_BASE_IOCTL_NR 0xF8
475#define HSMP_IOCTL_CMD _IOWR(HSMP_BASE_IOCTL_NR, 0, struct hsmp_message)
476
477#endif /*_ASM_X86_AMD_HSMP_H_*/