1/* $OpenBSD: specialreg.h,v 1.86 2026/04/19 01:10:28 jsg Exp $ */
2/* $NetBSD: specialreg.h,v 1.7 1994/10/27 04:16:26 cgd Exp $ */
3
4/*-
5 * Copyright (c) 1991 The Regents of the University of California.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of the University nor the names of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written permission.
19 *
20 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
24 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
25 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
26 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
28 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
29 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * SUCH DAMAGE.
31 *
32 * @(#)specialreg.h 7.1 (Berkeley) 5/9/91
33 */
34
35/*
36 * Bits in 386 special registers:
37 */
38#define CR0_PE 0x00000001 /* Protected mode Enable */
39#define CR0_MP 0x00000002 /* "Math" Present (NPX or NPX emulator) */
40#define CR0_EM 0x00000004 /* EMulate non-NPX coproc. (trap ESC only) */
41#define CR0_TS 0x00000008 /* Task Switched (if MP, trap ESC and WAIT) */
42#define CR0_ET 0x00000010 /* Extension Type (387 (if set) vs 287) */
43#define CR0_PG 0x80000000 /* PaGing enable */
44
45/*
46 * Bits in 486 special registers:
47 */
48#define CR0_NE 0x00000020 /* Numeric Error enable (EX16 vs IRQ13) */
49#define CR0_WP 0x00010000 /* Write Protect (honor PG_RW in all modes) */
50#define CR0_AM 0x00040000 /* Alignment Mask (set to enable AC flag) */
51#define CR0_NW 0x20000000 /* Not Write-through */
52#define CR0_CD 0x40000000 /* Cache Disable */
53
54/*
55 * bits in CR3
56 */
57#define CR3_PWT (1ULL << 3)
58#define CR3_PCD (1ULL << 4)
59
60/*
61 * bits in the pentiums %cr4 register:
62 */
63
64#define CR4_VME 0x00000001 /* virtual 8086 mode extension enable */
65#define CR4_PVI 0x00000002 /* protected mode virtual interrupt enable */
66#define CR4_TSD 0x00000004 /* restrict RDTSC instruction to cpl 0 only */
67#define CR4_DE 0x00000008 /* debugging extension */
68#define CR4_PSE 0x00000010 /* large (4MB) page size enable */
69#define CR4_PAE 0x00000020 /* physical address extension enable */
70#define CR4_MCE 0x00000040 /* machine check enable */
71#define CR4_PGE 0x00000080 /* page global enable */
72#define CR4_PCE 0x00000100 /* enable RDPMC instruction for all cpls */
73#define CR4_OSFXSR 0x00000200 /* enable fxsave/fxrestor and SSE */
74#define CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
75#define CR4_UMIP 0x00000800 /* user mode instruction prevention */
76#define CR4_VMXE 0x00002000 /* enable virtual machine operation */
77#define CR4_SMXE 0x00004000 /* enable safe mode operation */
78#define CR4_FSGSBASE 0x00010000 /* enable {RD,WR}{FS,GS}BASE ops */
79#define CR4_PCIDE 0x00020000 /* enable process-context IDs */
80#define CR4_OSXSAVE 0x00040000 /* enable XSAVE and extended states */
81#define CR4_SMEP 0x00100000 /* supervisor mode exec protection */
82#define CR4_SMAP 0x00200000 /* supervisor mode access prevention */
83#define CR4_PKE 0x00400000 /* protection key enable */
84
85/*
86 * CPUID "features" bits (CPUID function 0x1):
87 * EDX bits, then ECX bits
88 */
89
90#define CPUID_FPU 0x00000001 /* processor has an FPU? */
91#define CPUID_VME 0x00000002 /* has virtual mode (%cr4's VME/PVI) */
92#define CPUID_DE 0x00000004 /* has debugging extension */
93#define CPUID_PSE 0x00000008 /* has 4MB page size extension */
94#define CPUID_TSC 0x00000010 /* has time stamp counter */
95#define CPUID_MSR 0x00000020 /* has model specific registers */
96#define CPUID_PAE 0x00000040 /* has phys address extension */
97#define CPUID_MCE 0x00000080 /* has machine check exception */
98#define CPUID_CX8 0x00000100 /* has CMPXCHG8B instruction */
99#define CPUID_APIC 0x00000200 /* has enabled APIC */
100#define CPUID_SYS1 0x00000400 /* has SYSCALL/SYSRET inst. (Cyrix) */
101#define CPUID_SEP 0x00000800 /* has SYSCALL/SYSRET inst. (AMD/Intel) */
102#define CPUID_MTRR 0x00001000 /* has memory type range register */
103#define CPUID_PGE 0x00002000 /* has page global extension */
104#define CPUID_MCA 0x00004000 /* has machine check architecture */
105#define CPUID_CMOV 0x00008000 /* has CMOVcc instruction */
106#define CPUID_PAT 0x00010000 /* has page attribute table */
107#define CPUID_PSE36 0x00020000 /* has 36bit page size extension */
108#define CPUID_PSN 0x00040000 /* has processor serial number */
109#define CPUID_CFLUSH 0x00080000 /* CFLUSH insn supported */
110#define CPUID_B20 0x00100000 /* reserved */
111#define CPUID_DS 0x00200000 /* Debug Store */
112#define CPUID_ACPI 0x00400000 /* ACPI performance modulation regs */
113#define CPUID_MMX 0x00800000 /* has MMX instructions */
114#define CPUID_FXSR 0x01000000 /* has FXRSTOR instruction */
115#define CPUID_SSE 0x02000000 /* has streaming SIMD extensions */
116#define CPUID_SSE2 0x04000000 /* has streaming SIMD extensions #2 */
117#define CPUID_SS 0x08000000 /* self-snoop */
118#define CPUID_HTT 0x10000000 /* Hyper-Threading Technology */
119#define CPUID_TM 0x20000000 /* thermal monitor (TCC) */
120#define CPUID_B30 0x40000000 /* reserved */
121#define CPUID_PBE 0x80000000 /* Pending Break Enabled restarts clock */
122
123#define CPUIDECX_SSE3 0x00000001 /* streaming SIMD extensions #3 */
124#define CPUIDECX_PCLMUL 0x00000002 /* Carryless Multiplication */
125#define CPUIDECX_DTES64 0x00000004 /* 64bit debug store */
126#define CPUIDECX_MWAIT 0x00000008 /* Monitor/Mwait */
127#define CPUIDECX_DSCPL 0x00000010 /* CPL Qualified Debug Store */
128#define CPUIDECX_VMX 0x00000020 /* Virtual Machine Extensions */
129#define CPUIDECX_SMX 0x00000040 /* Safer Mode Extensions */
130#define CPUIDECX_EST 0x00000080 /* enhanced SpeedStep */
131#define CPUIDECX_TM2 0x00000100 /* thermal monitor 2 */
132#define CPUIDECX_SSSE3 0x00000200 /* Supplemental Streaming SIMD Ext. 3 */
133#define CPUIDECX_CNXTID 0x00000400 /* Context ID */
134#define CPUIDECX_SDBG 0x00000800 /* Silicon debug capability */
135#define CPUIDECX_FMA3 0x00001000 /* Fused Multiply Add */
136#define CPUIDECX_CX16 0x00002000 /* has CMPXCHG16B instruction */
137#define CPUIDECX_XTPR 0x00004000 /* xTPR Update Control */
138#define CPUIDECX_PDCM 0x00008000 /* Perfmon and Debug Capability */
139#define CPUIDECX_PCID 0x00020000 /* Process-context ID Capability */
140#define CPUIDECX_DCA 0x00040000 /* Direct Cache Access */
141#define CPUIDECX_SSE41 0x00080000 /* Streaming SIMD Extensions 4.1 */
142#define CPUIDECX_SSE42 0x00100000 /* Streaming SIMD Extensions 4.2 */
143#define CPUIDECX_X2APIC 0x00200000 /* Extended xAPIC Support */
144#define CPUIDECX_MOVBE 0x00400000 /* MOVBE Instruction */
145#define CPUIDECX_POPCNT 0x00800000 /* POPCNT Instruction */
146#define CPUIDECX_DEADLINE 0x01000000 /* APIC one-shot via deadline */
147#define CPUIDECX_AES 0x02000000 /* AES Instruction */
148#define CPUIDECX_XSAVE 0x04000000 /* XSAVE/XSTOR States */
149#define CPUIDECX_OSXSAVE 0x08000000 /* OSXSAVE */
150#define CPUIDECX_AVX 0x10000000 /* Advanced Vector Extensions */
151#define CPUIDECX_F16C 0x20000000 /* 16bit fp conversion */
152#define CPUIDECX_RDRAND 0x40000000 /* RDRAND instruction */
153#define CPUIDECX_HV 0x80000000 /* Running on hypervisor */
154
155/*
156 * "Structured Extended Feature Flags Parameters" (CPUID function 0x7, leaf 0)
157 * EBX bits
158 */
159#define SEFF0EBX_FSGSBASE 0x00000001 /* {RD,WR}[FG]SBASE instructions */
160#define SEFF0EBX_TSC_ADJUST 0x00000002 /* Has IA32_TSC_ADJUST MSR */
161#define SEFF0EBX_SGX 0x00000004 /* Software Guard Extensions */
162#define SEFF0EBX_BMI1 0x00000008 /* advanced bit manipulation */
163#define SEFF0EBX_HLE 0x00000010 /* Hardware Lock Elision */
164#define SEFF0EBX_AVX2 0x00000020 /* Advanced Vector Extensions 2 */
165#define SEFF0EBX_SMEP 0x00000080 /* Supervisor mode exec protection */
166#define SEFF0EBX_BMI2 0x00000100 /* advanced bit manipulation */
167#define SEFF0EBX_ERMS 0x00000200 /* Enhanced REP MOVSB/STOSB */
168#define SEFF0EBX_INVPCID 0x00000400 /* INVPCID instruction */
169#define SEFF0EBX_RTM 0x00000800 /* Restricted Transactional Memory */
170#define SEFF0EBX_PQM 0x00001000 /* Quality of Service Monitoring */
171#define SEFF0EBX_MPX 0x00004000 /* Memory Protection Extensions */
172#define SEFF0EBX_AVX512F 0x00010000 /* AVX-512 foundation inst */
173#define SEFF0EBX_AVX512DQ 0x00020000 /* AVX-512 double/quadword */
174#define SEFF0EBX_RDSEED 0x00040000 /* RDSEED instruction */
175#define SEFF0EBX_ADX 0x00080000 /* ADCX/ADOX instructions */
176#define SEFF0EBX_SMAP 0x00100000 /* Supervisor mode access prevent */
177#define SEFF0EBX_AVX512IFMA 0x00200000 /* AVX-512 integer mult-add */
178#define SEFF0EBX_PCOMMIT 0x00400000 /* Persistent commit inst */
179#define SEFF0EBX_CLFLUSHOPT 0x00800000 /* cache line flush */
180#define SEFF0EBX_CLWB 0x01000000 /* cache line write back */
181#define SEFF0EBX_PT 0x02000000 /* Processor Trace */
182#define SEFF0EBX_AVX512PF 0x04000000 /* AVX-512 prefetch */
183#define SEFF0EBX_AVX512ER 0x08000000 /* AVX-512 exp/reciprocal */
184#define SEFF0EBX_AVX512CD 0x10000000 /* AVX-512 conflict detection */
185#define SEFF0EBX_SHA 0x20000000 /* SHA Extensions */
186#define SEFF0EBX_AVX512BW 0x40000000 /* AVX-512 byte/word inst */
187#define SEFF0EBX_AVX512VL 0x80000000 /* AVX-512 vector len inst */
188/* SEFF ECX bits */
189#define SEFF0ECX_PREFETCHWT1 0x00000001 /* PREFETCHWT1 instruction */
190#define SEFF0ECX_AVX512VBMI 0x00000002 /* AVX-512 vector bit inst */
191#define SEFF0ECX_UMIP 0x00000004 /* UMIP support */
192#define SEFF0ECX_PKU 0x00000008 /* Page prot keys for user mode */
193#define SEFF0ECX_WAITPKG 0x00000020 /* UMONITOR/UMWAIT/TPAUSE insns */
194/* SEFF EDX bits */
195#define SEFF0EDX_AVX512_4FNNIW 0x00000004 /* AVX-512 neural network insns */
196#define SEFF0EDX_AVX512_4FMAPS 0x00000008 /* AVX-512 mult accum single prec */
197#define SEFF0EDX_SRBDS_CTRL 0x00000200 /* MCU_OPT_CTRL MSR */
198#define SEFF0EDX_MD_CLEAR 0x00000400 /* Microarch Data Clear */
199#define SEFF0EDX_TSXFA 0x00002000 /* TSX Forced Abort */
200#define SEFF0EDX_IBRS 0x04000000 /* IBRS / IBPB Speculation Control */
201#define SEFF0EDX_STIBP 0x08000000 /* STIBP Speculation Control */
202#define SEFF0EDX_L1DF 0x10000000 /* L1D_FLUSH */
203#define SEFF0EDX_ARCH_CAP 0x20000000 /* Has IA32_ARCH_CAPABILITIES MSR */
204#define SEFF0EDX_SSBD 0x80000000 /* Spec Store Bypass Disable */
205
206/*
207 * Thermal and Power Management (CPUID function 0x6) EAX bits
208 */
209#define TPM_SENSOR 0x00000001 /* Digital temp sensor */
210#define TPM_ARAT 0x00000004 /* APIC Timer Always Running */
211
212/*
213 * "Architectural Performance Monitoring" bits (CPUID function 0x0a):
214 * EAX bits
215 */
216
217#define CPUIDEAX_VERID 0x000000ff
218#define CPUIDEAX_NUM_GC(cpuid) (((cpuid) >> 8) & 0x000000ff)
219#define CPUIDEAX_BIT_GC(cpuid) (((cpuid) >> 16) & 0x000000ff)
220#define CPUIDEAX_LEN_EBX(cpuid) (((cpuid) >> 24) & 0x000000ff)
221
222#define CPUIDEBX_EVT_CORE (1 << 0) /* Core cycle */
223#define CPUIDEBX_EVT_INST (1 << 1) /* Instruction retired */
224#define CPUIDEBX_EVT_REFR (1 << 2) /* Reference cycles */
225#define CPUIDEBX_EVT_CACHE_REF (1 << 3) /* Last-level cache ref. */
226#define CPUIDEBX_EVT_CACHE_MIS (1 << 4) /* Last-level cache miss. */
227#define CPUIDEBX_EVT_BRANCH_INST (1 << 5) /* Branch instruction ret. */
228#define CPUIDEBX_EVT_BRANCH_MISP (1 << 6) /* Branch mispredict ret. */
229
230#define CPUIDEDX_NUM_FC(cpuid) (((cpuid) >> 0) & 0x0000001f)
231#define CPUIDEDX_BIT_FC(cpuid) (((cpuid) >> 5) & 0x000000ff)
232
233/*
234 * CPUID "extended features" bits (CPUID function 0x80000001):
235 * EDX bits, then ECX bits
236 */
237
238#define CPUID_MPC 0x00080000 /* Multiprocessing Capable */
239#define CPUID_NXE 0x00100000 /* No-Execute Extension */
240#define CPUID_MMXX 0x00400000 /* AMD MMX Extensions */
241#define CPUID_FFXSR 0x02000000 /* fast FP/MMX save/restore */
242#define CPUID_PAGE1GB 0x04000000 /* 1-GByte pages */
243#define CPUID_RDTSCP 0x08000000 /* RDTSCP / IA32_TSC_AUX available */
244#define CPUID_LONG 0x20000000 /* long mode */
245#define CPUID_3DNOW2 0x40000000 /* 3DNow! Instruction Extension */
246#define CPUID_3DNOW 0x80000000 /* 3DNow! Instructions */
247
248#define CPUIDECX_LAHF 0x00000001 /* LAHF and SAHF instructions */
249#define CPUIDECX_CMPLEG 0x00000002 /* Core MP legacy mode */
250#define CPUIDECX_SVM 0x00000004 /* Secure Virtual Machine */
251#define CPUIDECX_EAPICSP 0x00000008 /* Extended APIC space */
252#define CPUIDECX_AMCR8 0x00000010 /* LOCK MOV CR0 means MOV CR8 */
253#define CPUIDECX_ABM 0x00000020 /* LZCNT instruction */
254#define CPUIDECX_SSE4A 0x00000040 /* SSE4-A instruction set */
255#define CPUIDECX_MASSE 0x00000080 /* Misaligned SSE mode */
256#define CPUIDECX_3DNOWP 0x00000100 /* 3DNowPrefetch */
257#define CPUIDECX_OSVW 0x00000200 /* OS visible workaround */
258#define CPUIDECX_IBS 0x00000400 /* Instruction based sampling */
259#define CPUIDECX_XOP 0x00000800 /* Extended operating support */
260#define CPUIDECX_SKINIT 0x00001000 /* SKINIT and STGI are supported */
261#define CPUIDECX_WDT 0x00002000 /* Watchdog timer */
262/* Reserved 0x00004000 */
263#define CPUIDECX_LWP 0x00008000 /* Lightweight profiling support */
264#define CPUIDECX_FMA4 0x00010000 /* 4-operand FMA instructions */
265#define CPUIDECX_TCE 0x00020000 /* Translation Cache Extension */
266/* Reserved 0x00040000 */
267#define CPUIDECX_NODEID 0x00080000 /* Support for MSRC001C */
268/* Reserved 0x00100000 */
269#define CPUIDECX_TBM 0x00200000 /* Trailing bit manipulation instruction */
270#define CPUIDECX_TOPEXT 0x00400000 /* Topology extensions support */
271#define CPUIDECX_CPCTR 0x00800000 /* core performance counter ext */
272#define CPUIDECX_DBKP 0x04000000 /* DataBreakpointExtension */
273#define CPUIDECX_PERFTSC 0x08000000 /* performance time-stamp counter */
274#define CPUIDECX_PCTRL3 0x10000000 /* L3 performance counter ext */
275#define CPUIDECX_MWAITX 0x20000000 /* MWAITX/MONITORX */
276
277/*
278 * "Advanced Power Management Information" bits (CPUID function 0x80000007):
279 * EDX bits.
280 */
281
282#define CPUIDEDX_ITSC (1 << 8) /* Invariant TSC */
283
284/*
285 * AMD CPUID function 0x80000008 EBX bits
286 */
287#define CPUIDEBX_IBPB (1ULL << 12) /* Speculation Control IBPB */
288#define CPUIDEBX_IBRS (1ULL << 14) /* Speculation Control IBRS */
289#define CPUIDEBX_STIBP (1ULL << 15) /* Speculation Control STIBP */
290#define CPUIDEBX_IBRS_ALWAYSON (1ULL << 16) /* IBRS always on mode */
291#define CPUIDEBX_STIBP_ALWAYSON (1ULL << 17) /* STIBP always on mode */
292#define CPUIDEBX_IBRS_PREF (1ULL << 18) /* IBRS preferred */
293#define CPUIDEBX_SSBD (1ULL << 24) /* Speculation Control SSBD */
294#define CPUIDEBX_VIRT_SSBD (1ULL << 25) /* Virt Spec Control SSBD */
295#define CPUIDEBX_SSBD_NOTREQ (1ULL << 26) /* SSBD not required */
296
297#define CPUID2FAMILY(cpuid) (((cpuid) >> 8) & 15)
298#define CPUID2MODEL(cpuid) (((cpuid) >> 4) & 15)
299#define CPUID2STEPPING(cpuid) ((cpuid) & 15)
300
301#define CPUID(code, eax, ebx, ecx, edx) \
302 __asm volatile("cpuid" \
303 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
304 : "a" (code))
305#define CPUID_LEAF(code, leaf, eax, ebx, ecx, edx) \
306 __asm volatile("cpuid" \
307 : "=a" (eax), "=b" (ebx), "=c" (ecx), "=d" (edx) \
308 : "a" (code), "c" (leaf))
309
310
311/*
312 * Model-specific registers for the i386 family
313 */
314#define MSR_P5_MC_ADDR 0x000
315#define MSR_P5_MC_TYPE 0x001
316#define MSR_TSC 0x010
317#define P5MSR_CTRSEL 0x011 /* P5 only (trap on P6) */
318#define P5MSR_CTR0 0x012 /* P5 only (trap on P6) */
319#define P5MSR_CTR1 0x013 /* P5 only (trap on P6) */
320#define MSR_PLATFORM_ID 0x017 /* Platform ID for microcode */
321#define MSR_APICBASE 0x01b
322#define APICBASE_BSP 0x100
323#define APICBASE_ENABLE_X2APIC 0x400
324#define APICBASE_GLOBAL_ENABLE 0x800
325#define MSR_EBL_CR_POWERON 0x02a
326#define MSR_EBC_FREQUENCY_ID 0x02c /* Pentium 4 only */
327#define MSR_TEST_CTL 0x033
328#define MSR_IA32_FEATURE_CONTROL 0x03a
329#define MSR_SPEC_CTRL 0x048 /* Speculation Control IBRS / STIBP */
330#define SPEC_CTRL_IBRS (1ULL << 0)
331#define SPEC_CTRL_STIBP (1ULL << 1)
332#define SPEC_CTRL_SSBD (1ULL << 2)
333#define MSR_PRED_CMD 0x049 /* Speculation Control IBPB */
334#define PRED_CMD_IBPB (1ULL << 0)
335#define MSR_BIOS_UPDT_TRIG 0x079
336#define MSR_BBL_CR_D0 0x088 /* PII+ only */
337#define MSR_BBL_CR_D1 0x089 /* PII+ only */
338#define MSR_BBL_CR_D2 0x08a /* PII+ only */
339#define MSR_BIOS_SIGN 0x08b
340#define MSR_PERFCTR0 0x0c1
341#define MSR_PERFCTR1 0x0c2
342#define P6MSR_CTR0 0x0c1
343#define P6MSR_CTR1 0x0c2
344#define MSR_FSB_FREQ 0x0cd /* Core Duo/Solo only */
345#define MSR_MTRRcap 0x0fe
346#define MTRRcap_FIXED 0x100 /* bit 8 - fixed MTRRs supported */
347#define MTRRcap_WC 0x400 /* bit 10 - WC type supported */
348#define MTRRcap_SMRR 0x800 /* bit 11 - SMM range reg supported */
349#define MSR_ARCH_CAPABILITIES 0x10a
350#define ARCH_CAP_RDCL_NO (1 << 0) /* Meltdown safe */
351#define ARCH_CAP_IBRS_ALL (1 << 1) /* enhanced IBRS */
352#define ARCH_CAP_RSBA (1 << 2) /* RSB Alternate */
353#define ARCH_CAP_SKIP_L1DFL_VMENTRY (1 << 3)
354#define ARCH_CAP_SSB_NO (1 << 4) /* Spec St Byp safe */
355#define ARCH_CAP_MDS_NO (1 << 5) /* microarch data-sampling */
356#define ARCH_CAP_IF_PSCHANGE_MC_NO (1 << 6) /* PS MCE safe */
357#define ARCH_CAP_TSX_CTRL (1 << 7) /* has TSX_CTRL MSR */
358#define ARCH_CAP_TAA_NO (1 << 8) /* TSX AA safe */
359#define ARCH_CAP_MCU_CONTROL (1 << 9) /* has MCU_CTRL MSR */
360#define ARCH_CAP_MISC_PACKAGE_CTLS (1 << 10) /* has MISC_PKG_CTLS MSR */
361#define ARCH_CAP_ENERGY_FILTERING_CTL (1 << 11) /* r/w energy fltring bit */
362#define ARCH_CAP_DOITM (1 << 12) /* Data oprnd indpdnt tmng */
363#define ARCH_CAP_SBDR_SSDP_NO (1 << 13) /* SBDR/SSDP safe */
364#define ARCH_CAP_FBSDP_NO (1 << 14) /* FBSDP safe */
365#define ARCH_CAP_PSDP_NO (1 << 15) /* PSDP safe */
366#define ARCH_CAP_FB_CLEAR (1 << 17) /* MD_CLEAR covers FB */
367#define ARCH_CAP_FB_CLEAR_CTRL (1 << 18)
368#define ARCH_CAP_RRSBA (1 << 19) /* has RRSBA if not dis */
369#define ARCH_CAP_BHI_NO (1 << 20) /* BHI safe */
370#define ARCH_CAP_XAPIC_DISABLE_STATUS (1 << 21) /* can disable xAPIC */
371#define ARCH_CAP_OVERCLOCKING_STATUS (1 << 23) /* has OVRCLCKNG_STAT MSR */
372#define ARCH_CAP_PBRSB_NO (1 << 24) /* PBSR safe */
373#define ARCH_CAP_GDS_CTRL (1 << 25) /* has GDS_MITG_DIS/LOCK */
374#define ARCH_CAP_GDS_NO (1 << 26) /* GDS safe */
375#define MSR_FLUSH_CMD 0x10b
376#define FLUSH_CMD_L1D_FLUSH (1ULL << 0)
377#define MSR_BBL_CR_ADDR 0x116 /* PII+ only */
378#define MSR_BBL_CR_DECC 0x118 /* PII+ only */
379#define MSR_BBL_CR_CTL 0x119 /* PII+ only */
380#define MSR_BBL_CR_TRIG 0x11a /* PII+ only */
381#define MSR_BBL_CR_BUSY 0x11b /* PII+ only */
382#define MSR_BBL_CR_CTR3 0x11e /* PII+ only */
383#define MSR_TSX_CTRL 0x122
384#define TSX_CTRL_RTM_DISABLE (1ULL << 0)
385#define TSX_CTRL_TSX_CPUID_CLEAR (1ULL << 1)
386#define MSR_MCU_OPT_CTRL 0x123
387#define RNGDS_MITG_DIS (1ULL << 0)
388#define MSR_SYSENTER_CS 0x174
389#define MSR_SYSENTER_ESP 0x175
390#define MSR_SYSENTER_EIP 0x176
391#define MSR_MCG_CAP 0x179
392#define MSR_MCG_STATUS 0x17a
393#define MSR_MCG_CTL 0x17b
394#define P6MSR_CTRSEL0 0x186
395#define P6MSR_CTRSEL1 0x187
396#define MSR_PERF_STATUS 0x198 /* Pentium M */
397#define MSR_PERF_CTL 0x199 /* Pentium M */
398#define PERF_CTL_TURBO 0x100000000ULL /* bit 32 - turbo mode */
399#define MSR_THERM_CONTROL 0x19a
400#define MSR_THERM_INTERRUPT 0x19b
401#define MSR_THERM_STATUS 0x19c
402#define MSR_THERM_STATUS_VALID_BIT 0x80000000
403#define MSR_THERM_STATUS_TEMP(msr) ((msr >> 16) & 0x7f)
404#define MSR_THERM2_CTL 0x19d /* Pentium M */
405#define MSR_MISC_ENABLE 0x1a0
406/*
407 * MSR_MISC_ENABLE (0x1a0)
408 *
409 * Enable Fast Strings: enables fast REP MOVS/REP STORS (R/W)
410 * Enable TCC: Enable automatic thermal control circuit (R/W)
411 * Performance monitoring available: 1 if enabled (R/O)
412 * Branch trace storage unavailable: 1 if unsupported (R/O)
413 * Processor event based sampling unavailable: 1 if unsupported (R/O)
414 * Enhanced Intel SpeedStep technology enable: 1 to enable (R/W)
415 * Enable monitor FSM: 1 to enable MONITOR/MWAIT (R/W)
416 * Limit CPUID maxval: 1 to limit CPUID leaf nodes to 0x2 and lower (R/W)
417 * Enable xTPR message disable: 1 to disable xTPR messages
418 * XD bit disable: 1 to disable NX capability (bit 34, or bit 2 of %edx/%rdx)
419 */
420#define MISC_ENABLE_FAST_STRINGS (1 << 0)
421#define MISC_ENABLE_TCC (1 << 3)
422#define MISC_ENABLE_PERF_MON_AVAILABLE (1 << 7)
423#define MISC_ENABLE_BTS_UNAVAILABLE (1 << 11)
424#define MISC_ENABLE_PEBS_UNAVAILABLE (1 << 12)
425#define MISC_ENABLE_EIST_ENABLED (1 << 16)
426#define MISC_ENABLE_ENABLE_MONITOR_FSM (1 << 18)
427#define MISC_ENABLE_LIMIT_CPUID_MAXVAL (1 << 22)
428#define MISC_ENABLE_xTPR_MESSAGE_DISABLE (1 << 23)
429#define MISC_ENABLE_XD_BIT_DISABLE (1 << 2)
430/*
431 * for Core i Series and newer Xeons, see
432 * http://www.intel.com/content/dam/www/public/us/en/
433 * documents/white-papers/cpu-monitoring-dts-peci-paper.pdf
434 */
435#define MSR_TEMPERATURE_TARGET 0x1a2 /* Core i Series, Newer Xeons */
436#define MSR_TEMPERATURE_TARGET_TJMAX(r) (((r) >> 16) & 0xff)
437/*
438 * not documented anywhere, see intelcore_update_sensor()
439 * only available Core Duo and Core Solo Processors
440 */
441#define MSR_TEMPERATURE_TARGET_UNDOCUMENTED 0x0ee
442#define MSR_TEMPERATURE_TARGET_LOW_BIT_UNDOCUMENTED 0x40000000
443#define MSR_DEBUGCTLMSR 0x1d9
444#define MSR_LASTBRANCHFROMIP 0x1db
445#define MSR_LASTBRANCHTOIP 0x1dc
446#define MSR_LASTINTFROMIP 0x1dd
447#define MSR_LASTINTTOIP 0x1de
448#define MSR_ROB_CR_BKUPTMPDR6 0x1e0
449#define MSR_MTRRvarBase 0x200
450#define MSR_MTRRfix64K_00000 0x250
451#define MSR_MTRRfix16K_80000 0x258
452#define MSR_MTRRfix4K_C0000 0x268
453#define MSR_CR_PAT 0x277
454#define MSR_MTRRdefType 0x2ff
455#define MTRRdefType_FIXED_ENABLE 0x400 /* bit 10 - fixed MTRR enabled */
456#define MTRRdefType_ENABLE 0x800 /* bit 11 - MTRRs enabled */
457#define MSR_PERF_FIXED_CTR1 0x30a /* CPU_CLK_Unhalted.Core */
458#define MSR_PERF_FIXED_CTR2 0x30b /* CPU_CLK.Unhalted.Ref */
459#define MSR_PERF_FIXED_CTR_CTRL 0x38d
460#define MSR_PERF_FIXED_CTR_FC_DIS 0x0 /* disable counter */
461#define MSR_PERF_FIXED_CTR_FC_1 0x1 /* count ring 1 */
462#define MSR_PERF_FIXED_CTR_FC_123 0x2 /* count rings 1,2,3 */
463#define MSR_PERF_FIXED_CTR_FC_ANY 0x3 /* count everything */
464#define MSR_PERF_FIXED_CTR_FC_MASK 0x3
465#define MSR_PERF_FIXED_CTR_FC(_i, _v) ((_v) << (4 * (_i)))
466#define MSR_PERF_FIXED_CTR_ANYTHR(_i) (0x4 << (4 * (_i)))
467#define MSR_PERF_FIXED_CTR_INT(_i) (0x8 << (4 * (_i)))
468#define MSR_PERF_GLOBAL_CTRL 0x38f
469#define MSR_PERF_GLOBAL_CTR1_EN (1ULL << 33)
470#define MSR_PERF_GLOBAL_CTR2_EN (1ULL << 34)
471#define MSR_MC0_CTL 0x400
472#define MSR_MC0_STATUS 0x401
473#define MSR_MC0_ADDR 0x402
474#define MSR_MC0_MISC 0x403
475#define MSR_MC1_CTL 0x404
476#define MSR_MC1_STATUS 0x405
477#define MSR_MC1_ADDR 0x406
478#define MSR_MC1_MISC 0x407
479#define MSR_MC2_CTL 0x408
480#define MSR_MC2_STATUS 0x409
481#define MSR_MC2_ADDR 0x40a
482#define MSR_MC2_MISC 0x40b
483#define MSR_MC4_CTL 0x40c
484#define MSR_MC4_STATUS 0x40d
485#define MSR_MC4_ADDR 0x40e
486#define MSR_MC4_MISC 0x40f
487#define MSR_MC3_CTL 0x410
488#define MSR_MC3_STATUS 0x411
489#define MSR_MC3_ADDR 0x412
490#define MSR_MC3_MISC 0x413
491
492/* VIA MSRs */
493#define MSR_CENT_TMTEMPERATURE 0x1423 /* Thermal monitor temperature */
494#define MSR_C7M_TMTEMPERATURE 0x1169
495
496/* AMD MSRs */
497#define MSR_K6_EPMR 0xc0000086
498#define MSR_K7_EVNTSEL0 0xc0010000
499#define MSR_K7_EVNTSEL1 0xc0010001
500#define MSR_K7_EVNTSEL2 0xc0010002
501#define MSR_K7_EVNTSEL3 0xc0010003
502#define MSR_K7_PERFCTR0 0xc0010004
503#define MSR_K7_PERFCTR1 0xc0010005
504#define MSR_K7_PERFCTR2 0xc0010006
505#define MSR_K7_PERFCTR3 0xc0010007
506
507/*
508 * AMD K8 (Opteron) MSRs.
509 */
510#define MSR_PATCH_LEVEL 0x0000008b
511#define MSR_SYSCFG 0xc0000010
512
513#define MSR_EFER 0xc0000080 /* Extended feature enable */
514#define EFER_SCE 0x00000001 /* SYSCALL extension */
515#define EFER_LME 0x00000100 /* Long Mode Active */
516#define EFER_LMA 0x00000400 /* Long Mode Enabled */
517#define EFER_NXE 0x00000800 /* No-Execute Enabled */
518#define EFER_SVME 0x00001000 /* SVM Enabled */
519
520#define MSR_STAR 0xc0000081 /* 32 bit syscall gate addr */
521#define MSR_LSTAR 0xc0000082 /* 64 bit syscall gate addr */
522#define MSR_CSTAR 0xc0000083 /* compat syscall gate addr */
523#define MSR_SFMASK 0xc0000084 /* flags to clear on syscall */
524
525#define MSR_FSBASE 0xc0000100 /* 64bit offset for fs: */
526#define MSR_GSBASE 0xc0000101 /* 64bit offset for gs: */
527#define MSR_KERNELGSBASE 0xc0000102 /* storage for swapgs ins */
528#define MSR_PATCH_LOADER 0xc0010020
529#define MSR_INT_PEN_MSG 0xc0010055 /* Interrupt pending message */
530
531#define MSR_FP_CFG 0xc0011028 /* Floating Point Configuration */
532#define FP_CFG_9 (1 << 9) /* FP-DSS chickenbit */
533#define MSR_DE_CFG 0xc0011029 /* Decode Configuration */
534#define DE_CFG_721 0x00000001 /* errata 721 */
535#define DE_CFG_SERIALIZE_LFENCE (1 << 1) /* Enable serializing lfence */
536#define DE_CFG_SERIALIZE_9 (1 << 9) /* Zenbleed chickenbit */
537
538#define IPM_C1E_CMP_HLT 0x10000000
539#define IPM_SMI_CMP_HLT 0x08000000
540
541/*
542 * These require a 'passcode' for access. See cpufunc.h.
543 */
544#define MSR_HWCR 0xc0010015
545#define HWCR_FFDIS 0x00000040
546
547#define MSR_NB_CFG 0xc001001f
548#define NB_CFG_DISIOREQLOCK 0x0000000000000004ULL
549#define NB_CFG_DISDATMSK 0x0000001000000000ULL
550
551#define MSR_LS_CFG 0xc0011020
552#define LS_CFG_DIS_LS2_SQUISH 0x02000000
553
554#define MSR_IC_CFG 0xc0011021
555#define IC_CFG_DIS_SEQ_PREFETCH 0x00000800
556
557#define MSR_DC_CFG 0xc0011022
558#define DC_CFG_DIS_CNV_WC_SSO 0x00000004
559#define DC_CFG_DIS_SMC_CHK_BUF 0x00000400
560
561#define MSR_BU_CFG 0xc0011023
562#define BU_CFG_THRL2IDXCMPDIS 0x0000080000000000ULL
563#define BU_CFG_WBPFSMCCHKDIS 0x0000200000000000ULL
564#define BU_CFG_WBENHWSBDIS 0x0001000000000000ULL
565
566/*
567 * Constants related to MTRRs
568 */
569#define MTRR_N64K 8 /* numbers of fixed-size entries */
570#define MTRR_N16K 16
571#define MTRR_N4K 64
572
573/*
574 * the following four 3-byte registers control the non-cacheable regions.
575 * These registers must be written as three separate bytes.
576 *
577 * NCRx+0: A31-A24 of starting address
578 * NCRx+1: A23-A16 of starting address
579 * NCRx+2: A15-A12 of starting address | NCR_SIZE_xx.
580 *
581 * The non-cacheable region's starting address must be aligned to the
582 * size indicated by the NCR_SIZE_xx field.
583 */
584#define NCR1 0xc4
585#define NCR2 0xc7
586#define NCR3 0xca
587#define NCR4 0xcd
588
589#define NCR_SIZE_0K 0
590#define NCR_SIZE_4K 1
591#define NCR_SIZE_8K 2
592#define NCR_SIZE_16K 3
593#define NCR_SIZE_32K 4
594#define NCR_SIZE_64K 5
595#define NCR_SIZE_128K 6
596#define NCR_SIZE_256K 7
597#define NCR_SIZE_512K 8
598#define NCR_SIZE_1M 9
599#define NCR_SIZE_2M 10
600#define NCR_SIZE_4M 11
601#define NCR_SIZE_8M 12
602#define NCR_SIZE_16M 13
603#define NCR_SIZE_32M 14
604#define NCR_SIZE_4G 15
605
606/*
607 * Performance monitor events.
608 *
609 * Note that 586-class and 686-class CPUs have different performance
610 * monitors available, and they are accessed differently:
611 *
612 * 686-class: `rdpmc' instruction
613 * 586-class: `rdmsr' instruction, CESR MSR
614 *
615 * The descriptions of these events are too lengthy to include here.
616 * See Appendix A of "Intel Architecture Software Developer's
617 * Manual, Volume 3: System Programming" for more information.
618 */
619
620/*
621 * 586-class CESR MSR format. Lower 16 bits is CTR0, upper 16 bits
622 * is CTR1.
623 */
624
625#define PMC5_CESR_EVENT 0x003f
626#define PMC5_CESR_OS 0x0040
627#define PMC5_CESR_USR 0x0080
628#define PMC5_CESR_E 0x0100
629#define PMC5_CESR_P 0x0200
630
631/*
632 * 686-class Event Selector MSR format.
633 */
634
635#define PMC6_EVTSEL_EVENT 0x000000ff
636#define PMC6_EVTSEL_UNIT 0x0000ff00
637#define PMC6_EVTSEL_UNIT_SHIFT 8
638#define PMC6_EVTSEL_USR (1 << 16)
639#define PMC6_EVTSEL_OS (1 << 17)
640#define PMC6_EVTSEL_E (1 << 18)
641#define PMC6_EVTSEL_PC (1 << 19)
642#define PMC6_EVTSEL_INT (1 << 20)
643#define PMC6_EVTSEL_EN (1 << 22) /* PerfEvtSel0 only */
644#define PMC6_EVTSEL_INV (1 << 23)
645#define PMC6_EVTSEL_COUNTER_MASK 0xff000000
646#define PMC6_EVTSEL_COUNTER_MASK_SHIFT 24
647
648/* Data Cache Unit */
649#define PMC6_DATA_MEM_REFS 0x43
650#define PMC6_DCU_LINES_IN 0x45
651#define PMC6_DCU_M_LINES_IN 0x46
652#define PMC6_DCU_M_LINES_OUT 0x47
653#define PMC6_DCU_MISS_OUTSTANDING 0x48
654
655/* Instruction Fetch Unit */
656#define PMC6_IFU_IFETCH 0x80
657#define PMC6_IFU_IFETCH_MISS 0x81
658#define PMC6_ITLB_MISS 0x85
659#define PMC6_IFU_MEM_STALL 0x86
660#define PMC6_ILD_STALL 0x87
661
662/* L2 Cache */
663#define PMC6_L2_IFETCH 0x28
664#define PMC6_L2_LD 0x29
665#define PMC6_L2_ST 0x2a
666#define PMC6_L2_LINES_IN 0x24
667#define PMC6_L2_LINES_OUT 0x26
668#define PMC6_L2_M_LINES_INM 0x25
669#define PMC6_L2_M_LINES_OUTM 0x27
670#define PMC6_L2_RQSTS 0x2e
671#define PMC6_L2_ADS 0x21
672#define PMC6_L2_DBUS_BUSY 0x22
673#define PMC6_L2_DBUS_BUSY_RD 0x23
674
675/* External Bus Logic */
676#define PMC6_BUS_DRDY_CLOCKS 0x62
677#define PMC6_BUS_LOCK_CLOCKS 0x63
678#define PMC6_BUS_REQ_OUTSTANDING 0x60
679#define PMC6_BUS_TRAN_BRD 0x65
680#define PMC6_BUS_TRAN_RFO 0x66
681#define PMC6_BUS_TRANS_WB 0x67
682#define PMC6_BUS_TRAN_IFETCH 0x68
683#define PMC6_BUS_TRAN_INVAL 0x69
684#define PMC6_BUS_TRAN_PWR 0x6a
685#define PMC6_BUS_TRANS_P 0x6b
686#define PMC6_BUS_TRANS_IO 0x6c
687#define PMC6_BUS_TRAN_DEF 0x6d
688#define PMC6_BUS_TRAN_BURST 0x6e
689#define PMC6_BUS_TRAN_ANY 0x70
690#define PMC6_BUS_TRAN_MEM 0x6f
691#define PMC6_BUS_DATA_RCV 0x64
692#define PMC6_BUS_BNR_DRV 0x61
693#define PMC6_BUS_HIT_DRV 0x7a
694#define PMC6_BUS_HITM_DRDV 0x7b
695#define PMC6_BUS_SNOOP_STALL 0x7e
696
697/* Floating Point Unit */
698#define PMC6_FLOPS 0xc1
699#define PMC6_FP_COMP_OPS_EXE 0x10
700#define PMC6_FP_ASSIST 0x11
701#define PMC6_MUL 0x12
702#define PMC6_DIV 0x12
703#define PMC6_CYCLES_DIV_BUSY 0x14
704
705/* Memory Ordering */
706#define PMC6_LD_BLOCKS 0x03
707#define PMC6_SB_DRAINS 0x04
708#define PMC6_MISALIGN_MEM_REF 0x05
709#define PMC6_EMON_KNI_PREF_DISPATCHED 0x07 /* P-III only */
710#define PMC6_EMON_KNI_PREF_MISS 0x4b /* P-III only */
711
712/* Instruction Decoding and Retirement */
713#define PMC6_INST_RETIRED 0xc0
714#define PMC6_UOPS_RETIRED 0xc2
715#define PMC6_INST_DECODED 0xd0
716#define PMC6_EMON_KNI_INST_RETIRED 0xd8
717#define PMC6_EMON_KNI_COMP_INST_RET 0xd9
718
719/* Interrupts */
720#define PMC6_HW_INT_RX 0xc8
721#define PMC6_CYCLES_INT_MASKED 0xc6
722#define PMC6_CYCLES_INT_PENDING_AND_MASKED 0xc7
723
724/* Branches */
725#define PMC6_BR_INST_RETIRED 0xc4
726#define PMC6_BR_MISS_PRED_RETIRED 0xc5
727#define PMC6_BR_TAKEN_RETIRED 0xc9
728#define PMC6_BR_MISS_PRED_TAKEN_RET 0xca
729#define PMC6_BR_INST_DECODED 0xe0
730#define PMC6_BTB_MISSES 0xe2
731#define PMC6_BR_BOGUS 0xe4
732#define PMC6_BACLEARS 0xe6
733
734/* Stalls */
735#define PMC6_RESOURCE_STALLS 0xa2
736#define PMC6_PARTIAL_RAT_STALLS 0xd2
737
738/* Segment Register Loads */
739#define PMC6_SEGMENT_REG_LOADS 0x06
740
741/* Clocks */
742#define PMC6_CPU_CLK_UNHALTED 0x79
743
744/* MMX Unit */
745#define PMC6_MMX_INSTR_EXEC 0xb0 /* Celeron, P-II, P-IIX only */
746#define PMC6_MMX_SAT_INSTR_EXEC 0xb1 /* P-II and P-III only */
747#define PMC6_MMX_UOPS_EXEC 0xb2 /* P-II and P-III only */
748#define PMC6_MMX_INSTR_TYPE_EXEC 0xb3 /* P-II and P-III only */
749#define PMC6_FP_MMX_TRANS 0xcc /* P-II and P-III only */
750#define PMC6_MMX_ASSIST 0xcd /* P-II and P-III only */
751#define PMC6_MMX_INSTR_RET 0xc3 /* P-II only */
752
753/* Segment Register Renaming */
754#define PMC6_SEG_RENAME_STALLS 0xd4 /* P-II and P-III only */
755#define PMC6_SEG_REG_RENAMES 0xd5 /* P-II and P-III only */
756#define PMC6_RET_SEG_RENAMES 0xd6 /* P-II and P-III only */
757
758/* VIA C3 crypto featureset: for i386_has_xcrypt */
759#define C3_HAS_AES 1 /* cpu has AES */
760#define C3_HAS_SHA 2 /* cpu has SHA1 & SHA256 */
761#define C3_HAS_MM 4 /* cpu has RSA instructions */
762#define C3_HAS_AESCTR 8 /* cpu has AES-CTR instructions */
763
764/* Centaur Extended Feature flags */
765#define C3_CPUID_HAS_RNG 0x000004
766#define C3_CPUID_DO_RNG 0x000008
767#define C3_CPUID_HAS_ACE 0x000040
768#define C3_CPUID_DO_ACE 0x000080
769#define C3_CPUID_HAS_ACE2 0x000100
770#define C3_CPUID_DO_ACE2 0x000200
771#define C3_CPUID_HAS_PHE 0x000400
772#define C3_CPUID_DO_PHE 0x000800
773#define C3_CPUID_HAS_PMM 0x001000
774#define C3_CPUID_DO_PMM 0x002000
775
776/* VIA C3 xcrypt-* instruction context control options */
777#define C3_CRYPT_CWLO_ROUND_M 0x0000000f
778#define C3_CRYPT_CWLO_ALG_M 0x00000070
779#define C3_CRYPT_CWLO_ALG_AES 0x00000000
780#define C3_CRYPT_CWLO_KEYGEN_M 0x00000080
781#define C3_CRYPT_CWLO_KEYGEN_HW 0x00000000
782#define C3_CRYPT_CWLO_KEYGEN_SW 0x00000080
783#define C3_CRYPT_CWLO_NORMAL 0x00000000
784#define C3_CRYPT_CWLO_INTERMEDIATE 0x00000100
785#define C3_CRYPT_CWLO_ENCRYPT 0x00000000
786#define C3_CRYPT_CWLO_DECRYPT 0x00000200
787#define C3_CRYPT_CWLO_KEY128 0x0000000a /* 128bit, 10 rds */
788#define C3_CRYPT_CWLO_KEY192 0x0000040c /* 192bit, 12 rds */
789#define C3_CRYPT_CWLO_KEY256 0x0000080e /* 256bit, 15 rds */
790
791/* Intel Silicon Debug */
792#define IA32_DEBUG_INTERFACE 0xc80
793#define IA32_DEBUG_INTERFACE_ENABLE 0x00000001
794#define IA32_DEBUG_INTERFACE_LOCK 0x40000000
795#define IA32_DEBUG_INTERFACE_MASK 0x80000000
796
797/*
798 * PAT
799 */
800#define PATENTRY(n, type) ((uint64_t)type << ((n) * 8))
801#define PAT_UC 0x0UL
802#define PAT_WC 0x1UL
803#define PAT_WT 0x4UL
804#define PAT_WP 0x5UL
805#define PAT_WB 0x6UL
806#define PAT_UCMINUS 0x7UL
807
808/*
809 * XSAVE subfeatures (cpuid 0xd, leaf 1)
810 */
811#define XSAVE_XSAVEOPT 0x1UL
812#define XSAVE_XSAVEC 0x2UL
813#define XSAVE_XGETBV1 0x4UL
814#define XSAVE_XSAVES 0x8UL