1/* $OpenBSD: intr.h,v 1.51 2025/04/25 12:47:37 mvs Exp $ */
2/* $NetBSD: intr.h,v 1.5 1996/05/13 06:11:28 mycroft Exp $ */
3
4/*
5 * Copyright (c) 1996 Charles M. Hannum. All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed by Charles M. Hannum.
18 * 4. The name of the author may not be used to endorse or promote products
19 * derived from this software without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33#ifndef _MACHINE_INTR_H_
34#define _MACHINE_INTR_H_
35
36#define __USE_MI_SOFTINTR
37
38#include <sys/softintr.h>
39#include <machine/intrdefs.h>
40
41#ifndef _LOCORE
42#include <sys/mutex.h>
43#include <machine/cpu.h>
44
45extern volatile u_int32_t lapic_tpr; /* Current interrupt priority level. */
46
47extern int imask[]; /* Bitmasks telling what interrupts are blocked. */
48extern int iunmask[]; /* Bitmasks telling what interrupts are accepted. */
49
50#define IMASK(level) imask[IPL(level)]
51#define IUNMASK(level) iunmask[IPL(level)]
52
53extern void Xspllower(void);
54
55extern int splraise(int);
56extern int spllower(int);
57extern void splx(int);
58extern void softintr(int);
59
60/*
61 * compiler barrier: prevent reordering of instructions.
62 * This prevents the compiler from reordering code around
63 * this "instruction", acting as a sequence point for code generation.
64 */
65
66#define __splbarrier() __asm volatile("":::"memory")
67
68/* SPL asserts */
69#ifdef DIAGNOSTIC
70/*
71 * Although this function is implemented in MI code, it must be in this MD
72 * header because we don't want this header to include MI includes.
73 */
74void splassert_fail(int, int, const char *);
75extern int splassert_ctl;
76void splassert_check(int, const char *);
77#define splassert(__wantipl) do { \
78 if (splassert_ctl > 0) { \
79 splassert_check(__wantipl, __func__); \
80 } \
81} while (0)
82#define splsoftassert(wantipl) splassert(wantipl)
83#else
84#define splassert(wantipl) do { /* nada */ } while (0)
85#define splsoftassert(wantipl) do { /* nada */ } while (0)
86#endif
87
88/*
89 * Define the splraise and splx code in macros, so that the code can be
90 * reused in a profiling build in a way that does not cause recursion.
91 */
92#define _SPLRAISE(ocpl, ncpl) \
93 ocpl = lapic_tpr; \
94 if (ncpl > ocpl) \
95 lapic_tpr = ncpl
96
97
98#define _SPLX(ncpl) \
99 lapic_tpr = ncpl; \
100 if (curcpu()->ci_ipending & IUNMASK(ncpl)) \
101 Xspllower()
102
103/*
104 * Hardware interrupt masks
105 */
106#define splbio() splraise(IPL_BIO)
107#define splnet() splraise(IPL_NET)
108#define spltty() splraise(IPL_TTY)
109#define splaudio() splraise(IPL_AUDIO)
110#define splclock() splraise(IPL_CLOCK)
111#define splstatclock() splclock()
112#define splipi() splraise(IPL_IPI)
113
114/*
115 * Software interrupt masks
116 */
117#define splsoftclock() splraise(IPL_SOFTCLOCK)
118#define splsoftnet() splraise(IPL_SOFTNET)
119#define splsofttty() splraise(IPL_SOFTTTY)
120
121/*
122 * Miscellaneous
123 */
124#define splvm() splraise(IPL_VM)
125#define splhigh() splraise(IPL_HIGH)
126#define splsched() splraise(IPL_SCHED)
127#define spl0() spllower(IPL_NONE)
128
129#include <machine/pic.h>
130
131struct cpu_info;
132
133void intr_barrier(void *);
134void intr_enable_wakeup(void);
135void intr_disable_wakeup(void);
136
137#ifdef MULTIPROCESSOR
138void i386_send_ipi(struct cpu_info *, int);
139int i386_fast_ipi(struct cpu_info *, int);
140void i386_broadcast_ipi(int);
141void i386_ipi_handler(void);
142void i386_setperf_ipi(struct cpu_info *);
143
144extern void (*ipifunc[I386_NIPI])(struct cpu_info *);
145#endif
146
147#endif /* !_LOCORE */
148
149#endif /* !_MACHINE_INTR_H_ */