1/*-
2 * SPDX-License-Identifier: BSD-4-Clause
3 *
4 * Copyright (c) 2002 David E. O'Brien. All rights reserved.
5 * Copyright (c) 1992, 1993
6 * The Regents of the University of California. All rights reserved.
7 *
8 * This code is derived from software contributed to Berkeley by
9 * the Systems Programming Group of the University of Utah Computer
10 * Science Department and Ralph Campbell.
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 * 1. Redistributions of source code must retain the above copyright
16 * notice, this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright
18 * notice, this list of conditions and the following disclaimer in the
19 * documentation and/or other materials provided with the distribution.
20 * 3. All advertising materials mentioning features or use of this software
21 * must display the following acknowledgement:
22 * This product includes software developed by the University of
23 * California, Berkeley and its contributors.
24 * 4. Neither the name of the University nor the names of its contributors
25 * may be used to endorse or promote products derived from this software
26 * without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
29 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
30 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
31 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
32 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * SUCH DAMAGE.
39 */
40
41#ifndef _AMD64_INCLUDE_PARAM_H_
42#define _AMD64_INCLUDE_PARAM_H_
43
44#include <machine/_align.h>
45
46/*
47 * Machine dependent constants for AMD64.
48 */
49
50#ifndef MACHINE
51#define MACHINE "amd64"
52#endif
53#ifndef MACHINE_ARCH
54#define MACHINE_ARCH "amd64"
55#endif
56#ifndef MACHINE_ARCH32
57#define MACHINE_ARCH32 "i386"
58#endif
59
60#ifdef SMP
61#ifndef MAXCPU
62#define MAXCPU 1024
63#endif
64#else
65#define MAXCPU 1
66#endif
67
68#ifndef MAXMEMDOM
69#define MAXMEMDOM 8
70#endif
71
72#define ALIGNBYTES _ALIGNBYTES
73#define ALIGN(p) _ALIGN(p)
74/*
75 * ALIGNED_POINTER is a boolean macro that checks whether an address
76 * is valid to fetch data elements of type t from on this architecture.
77 * This does not reflect the optimal alignment, just the possibility
78 * (within reasonable limits).
79 */
80#define ALIGNED_POINTER(p, t) 1
81
82/*
83 * CACHE_LINE_SIZE is the compile-time maximum cache line size for an
84 * architecture. It should be used with appropriate caution.
85 */
86#define CACHE_LINE_SHIFT 6
87#define CACHE_LINE_SIZE (1 << CACHE_LINE_SHIFT)
88
89/* Size of the level 1 page table units */
90#define NPTEPG (PAGE_SIZE/(sizeof (pt_entry_t)))
91#define NPTEPGSHIFT 9 /* LOG2(NPTEPG) */
92#define PAGE_SHIFT 12 /* LOG2(PAGE_SIZE) */
93#define PAGE_SIZE (1<<PAGE_SHIFT) /* bytes/page */
94#define PAGE_MASK (PAGE_SIZE-1)
95/* Size of the level 2 page directory units */
96#define NPDEPG (PAGE_SIZE/(sizeof (pd_entry_t)))
97#define NPDEPGSHIFT 9 /* LOG2(NPDEPG) */
98#define PDRSHIFT 21 /* LOG2(NBPDR) */
99#define NBPDR (1<<PDRSHIFT) /* bytes/page dir */
100#define PDRMASK (NBPDR-1)
101/* Size of the level 3 page directory pointer table units */
102#define NPDPEPG (PAGE_SIZE/(sizeof (pdp_entry_t)))
103#define NPDPEPGSHIFT 9 /* LOG2(NPDPEPG) */
104#define PDPSHIFT 30 /* LOG2(NBPDP) */
105#define NBPDP (1<<PDPSHIFT) /* bytes/page dir ptr table */
106#define PDPMASK (NBPDP-1)
107/* Size of the level 4 page-map level-4 table units */
108#define NPML4EPG (PAGE_SIZE/(sizeof (pml4_entry_t)))
109#define NPML4EPGSHIFT 9 /* LOG2(NPML4EPG) */
110#define PML4SHIFT 39 /* LOG2(NBPML4) */
111#define NBPML4 (1UL<<PML4SHIFT)/* bytes/page map lev4 table */
112#define PML4MASK (NBPML4-1)
113/* Size of the level 5 page-map level-5 table units */
114#define NPML5EPG (PAGE_SIZE/(sizeof (pml5_entry_t)))
115#define NPML5EPGSHIFT 9 /* LOG2(NPML5EPG) */
116#define PML5SHIFT 48 /* LOG2(NBPML5) */
117#define NBPML5 (1UL<<PML5SHIFT)/* bytes/page map lev5 table */
118#define PML5MASK (NBPML5-1)
119
120#define MAXPAGESIZES 3 /* maximum number of supported page sizes */
121
122#define IOPAGES 2 /* pages of i/o permission bitmap */
123/*
124 * I/O permission bitmap has a bit for each I/O port plus an additional
125 * byte at the end with all bits set. See section "I/O Permission Bit Map"
126 * in the Intel SDM for more details.
127 */
128#define IOPERM_BITMAP_SIZE (IOPAGES * PAGE_SIZE + 1)
129
130#ifndef KSTACK_PAGES
131#if defined(KASAN) || defined(KMSAN)
132#define KSTACK_PAGES 6
133#else
134#define KSTACK_PAGES 4 /* pages of kstack (with pcb) */
135#endif
136#endif
137#define KSTACK_GUARD_PAGES 1 /* pages of kstack guard; 0 disables */
138
139/*
140 * Mach derived conversion macros
141 */
142#define trunc_2mpage(x) ((unsigned long)(x) & ~PDRMASK)
143#define round_2mpage(x) ((((unsigned long)(x)) + PDRMASK) & ~PDRMASK)
144#define trunc_1gpage(x) ((unsigned long)(x) & ~PDPMASK)
145
146#define amd64_btop(x) ((unsigned long)(x) >> PAGE_SHIFT)
147#define amd64_ptob(x) ((unsigned long)(x) << PAGE_SHIFT)
148
149#define INKERNEL(va) \
150 (((va) >= kva_layout.dmap_low && (va) < kva_layout.dmap_high) || \
151 ((va) >= kva_layout.km_low && (va) < kva_layout.km_high))
152
153#define SC_TABLESIZE 1024 /* Must be power of 2. */
154
155#endif /* !_AMD64_INCLUDE_PARAM_H_ */