| 1 | /*- |
| 2 | * SPDX-License-Identifier: BSD-3-Clause |
| 3 | * |
| 4 | * Copyright (c) 2003 Peter Wemm. |
| 5 | * Copyright (c) 1991 Regents of the University of California. |
| 6 | * All rights reserved. |
| 7 | * |
| 8 | * This code is derived from software contributed to Berkeley by |
| 9 | * the Systems Programming Group of the University of Utah Computer |
| 10 | * Science Department and William Jolitz of UUNET Technologies Inc. |
| 11 | * |
| 12 | * Redistribution and use in source and binary forms, with or without |
| 13 | * modification, are permitted provided that the following conditions |
| 14 | * are met: |
| 15 | * 1. Redistributions of source code must retain the above copyright |
| 16 | * notice, this list of conditions and the following disclaimer. |
| 17 | * 2. Redistributions in binary form must reproduce the above copyright |
| 18 | * notice, this list of conditions and the following disclaimer in the |
| 19 | * documentation and/or other materials provided with the distribution. |
| 20 | * 3. Neither the name of the University nor the names of its contributors |
| 21 | * may be used to endorse or promote products derived from this software |
| 22 | * without specific prior written permission. |
| 23 | * |
| 24 | * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND |
| 25 | * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 27 | * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE |
| 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| 30 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| 31 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT |
| 32 | * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY |
| 33 | * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF |
| 34 | * SUCH DAMAGE. |
| 35 | * |
| 36 | * Derived from hp300 version by Mike Hibler, this version by William |
| 37 | * Jolitz uses a recursive map [a pde points to the page directory] to |
| 38 | * map the page tables using the pagetables themselves. This is done to |
| 39 | * reduce the impact on kernel virtual memory for lots of sparse address |
| 40 | * space, and to reduce the cost of memory to each process. |
| 41 | */ |
| 42 | |
| 43 | #ifndef _MACHINE_PTE_H_ |
| 44 | #define _MACHINE_PTE_H_ |
| 45 | |
| 46 | /* |
| 47 | * Page-directory and page-table entries follow this format, with a few |
| 48 | * of the fields not present here and there, depending on a lot of things. |
| 49 | */ |
| 50 | /* ---- Intel Nomenclature ---- */ |
| 51 | #define X86_PG_V 0x001 /* P Valid */ |
| 52 | #define X86_PG_RW 0x002 /* R/W Read/Write */ |
| 53 | #define X86_PG_U 0x004 /* U/S User/Supervisor */ |
| 54 | #define X86_PG_NC_PWT 0x008 /* PWT Write through */ |
| 55 | #define X86_PG_NC_PCD 0x010 /* PCD Cache disable */ |
| 56 | #define X86_PG_A 0x020 /* A Accessed */ |
| 57 | #define X86_PG_M 0x040 /* D Dirty */ |
| 58 | #define X86_PG_PS 0x080 /* PS Page size (0=4k,1=2M) */ |
| 59 | #define X86_PG_PTE_PAT 0x080 /* PAT PAT index */ |
| 60 | #define X86_PG_G 0x100 /* G Global */ |
| 61 | #define X86_PG_AVAIL1 0x200 /* / Available for system */ |
| 62 | #define X86_PG_AVAIL2 0x400 /* < programmers use */ |
| 63 | #define X86_PG_AVAIL3 0x800 /* \ */ |
| 64 | #define X86_PG_PDE_PAT 0x1000 /* PAT PAT index */ |
| 65 | #define X86_PG_PKU(idx) ((pt_entry_t)idx << 59) |
| 66 | #define X86_PG_NX (1ul<<63) /* No-execute */ |
| 67 | #define X86_PG_AVAIL(x) (1ul << (x)) |
| 68 | |
| 69 | /* Page level cache control fields used to determine the PAT type */ |
| 70 | #define X86_PG_PDE_CACHE (X86_PG_PDE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD) |
| 71 | #define X86_PG_PTE_CACHE (X86_PG_PTE_PAT | X86_PG_NC_PWT | X86_PG_NC_PCD) |
| 72 | |
| 73 | /* Protection keys indexes */ |
| 74 | #define PMAP_MAX_PKRU_IDX 0xf |
| 75 | #define X86_PG_PKU_MASK X86_PG_PKU(PMAP_MAX_PKRU_IDX) |
| 76 | |
| 77 | /* |
| 78 | * Intel extended page table (EPT) bit definitions. |
| 79 | */ |
| 80 | #define EPT_PG_READ 0x001 /* R Read */ |
| 81 | #define EPT_PG_WRITE 0x002 /* W Write */ |
| 82 | #define EPT_PG_EXECUTE 0x004 /* X Execute */ |
| 83 | #define EPT_PG_IGNORE_PAT 0x040 /* IPAT Ignore PAT */ |
| 84 | #define EPT_PG_PS 0x080 /* PS Page size */ |
| 85 | #define EPT_PG_A 0x100 /* A Accessed */ |
| 86 | #define EPT_PG_M 0x200 /* D Dirty */ |
| 87 | #define EPT_PG_MEMORY_TYPE(x) ((x) << 3) /* MT Memory Type */ |
| 88 | |
| 89 | #define PG_FRAME (0x000ffffffffff000ul) |
| 90 | #define PG_PS_FRAME (0x000fffffffe00000ul) |
| 91 | #define PG_PS_PDP_FRAME (0x000fffffc0000000ul) |
| 92 | |
| 93 | /* |
| 94 | * Page Protection Exception bits |
| 95 | */ |
| 96 | #define PGEX_P 0x01 /* Protection violation vs. not present */ |
| 97 | #define PGEX_W 0x02 /* during a Write cycle */ |
| 98 | #define PGEX_U 0x04 /* access from User mode (UPL) */ |
| 99 | #define PGEX_RSV 0x08 /* reserved PTE field is non-zero */ |
| 100 | #define PGEX_I 0x10 /* during an instruction fetch */ |
| 101 | #define PGEX_PK 0x20 /* protection key violation */ |
| 102 | #define PGEX_SGX 0x8000 /* SGX-related */ |
| 103 | |
| 104 | #endif |