1/* $NetBSD: mcontext.h,v 1.24.2.1 2026/07/19 15:57:26 martin Exp $ */
2
3/*-
4 * Copyright (c) 1999 The NetBSD Foundation, Inc.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to The NetBSD Foundation
8 * by Klaus Klein.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29 * POSSIBILITY OF SUCH DAMAGE.
30 */
31
32#ifndef _AMD64_MCONTEXT_H_
33#define _AMD64_MCONTEXT_H_
34
35#ifdef __x86_64__
36
37#include <machine/frame_regs.h>
38
39/*
40 * General register state
41 */
42#define GREG_OFFSETS(reg, REG, idx) _REG_##REG = idx,
43enum { _FRAME_GREG(GREG_OFFSETS) _NGREG = 26 };
44#undef GREG_OFFSETS
45
46typedef unsigned long __greg_t;
47typedef __greg_t __gregset_t[_NGREG];
48
49/* These names are for compatibility */
50#define _REG_URSP _REG_RSP
51#define _REG_RFL _REG_RFLAGS
52
53/*
54 * Floating point register state
55 * The format of __fpregset_t is that of the fxsave instruction
56 * which requires 16 byte alignment. However the mcontext version
57 * is never directly accessed.
58 */
59typedef union {
60 char __fxsave[512] __aligned(8);
61 struct {
62 /*
63 * `The XSAVE feature set does not use bytes 511:416;
64 * bytes 463:416 are reserved.'
65 *
66 * We take a part out of this to form a pointer to an
67 * external XSAVE area. This way, we can replicate the
68 * FXSAVE parts for the benefit of userland programs
69 * that aren't aware of the XSAVE pointer, have used
70 * the extended CPU registers (ymmN/zmmN/&c.), and want
71 * to examine the x87/SSE register state in a signal
72 * handler. The kernel does not use this part.
73 */
74 char __fxsave[416];
75 char __rsvd[48];
76 __greg_t __xsaveptr;
77 __greg_t __xsavelen;
78 char __pad[32];
79 } __xsave;
80} __fpregset_t;
81
82typedef struct {
83 __gregset_t __gregs;
84 __greg_t _mc_tlsbase;
85 __fpregset_t __fpregs;
86} mcontext_t;
87
88#define _UC_UCONTEXT_ALIGN (~0xf)
89
90/* AMD64 ABI 128-bytes "red zone". */
91#define _UC_MACHINE_SP(uc) ((uc)->uc_mcontext.__gregs[_REG_RSP] - 128)
92#define _UC_MACHINE_FP(uc) ((uc)->uc_mcontext.__gregs[_REG_RBP])
93#define _UC_MACHINE_PC(uc) ((uc)->uc_mcontext.__gregs[_REG_RIP])
94#define _UC_MACHINE_INTRV(uc) ((uc)->uc_mcontext.__gregs[_REG_RAX])
95
96#define _UC_MACHINE_SET_PC(uc, pc) _UC_MACHINE_PC(uc) = (pc)
97
98#define _UC_TLSBASE _UC_MD_BIT19
99#define _UC_XSAVE _UC_MD_BIT20
100
101/*
102 * mcontext extensions to handle signal delivery.
103 */
104#define _UC_SETSTACK _UC_MD_BIT16
105#define _UC_CLRSTACK _UC_MD_BIT17
106
107#define __UCONTEXT_SIZE 784
108
109#ifdef _KERNEL
110
111/*
112 * 32bit context definitions.
113 */
114
115#define _NGREG32 19
116typedef unsigned int __greg32_t;
117typedef __greg32_t __gregset32_t[_NGREG32];
118
119#define _REG32_GS 0
120#define _REG32_FS 1
121#define _REG32_ES 2
122#define _REG32_DS 3
123#define _REG32_EDI 4
124#define _REG32_ESI 5
125#define _REG32_EBP 6
126#define _REG32_ESP 7
127#define _REG32_EBX 8
128#define _REG32_EDX 9
129#define _REG32_ECX 10
130#define _REG32_EAX 11
131#define _REG32_TRAPNO 12
132#define _REG32_ERR 13
133#define _REG32_EIP 14
134#define _REG32_CS 15
135#define _REG32_EFL 16
136#define _REG32_UESP 17
137#define _REG32_SS 18
138
139#define _UC_MACHINE32_SP(uc) ((uc)->uc_mcontext.__gregs[_REG32_UESP])
140
141/*
142 * Floating point register state
143 */
144typedef struct {
145 union {
146 struct {
147 int __fp_state[27]; /* Environment and registers */
148 } __fpchip_state;
149 struct {
150 char __fp_xmm[512];
151 } __fp_xmm_state;
152 struct {
153 char __fxsave[416];
154 char __rsvd[48];
155 __greg32_t __xsaveptr;
156 __greg32_t __xsavelen;
157 char __pad[40];
158 } __xsave;
159 } __fp_reg_set;
160 int __fp_pad[33]; /* Historic padding */
161} __fpregset32_t;
162
163typedef struct {
164 __gregset32_t __gregs;
165 __fpregset32_t __fpregs;
166 uint32_t _mc_tlsbase;
167} mcontext32_t;
168
169#define _UC_FXSAVE _UC_MD_BIT5 /* FP state is in FXSAVE format in XMM space */
170
171#define _UC_MACHINE32_PAD 4
172#define __UCONTEXT32_SIZE 776
173
174#endif /* _KERNEL */
175
176#else /* __x86_64__ */
177
178#include <i386/mcontext.h>
179
180#endif /* __x86_64__ */
181
182#endif /* !_AMD64_MCONTEXT_H_ */