1/* $OpenBSD: intrdefs.h,v 1.25 2025/11/10 12:34:52 dlg Exp $ */
2/* $NetBSD: intrdefs.h,v 1.2 2003/05/04 22:01:56 fvdl Exp $ */
3
4#ifndef _AMD64_INTRDEFS_H
5#define _AMD64_INTRDEFS_H
6
7/*
8 * Interrupt priority levels.
9 *
10 * There are tty, network and disk drivers that use free() at interrupt
11 * time, so imp > (tty | net | bio).
12 *
13 * Since run queues may be manipulated by both the statclock and tty,
14 * network, and disk drivers, clock > imp.
15 *
16 * IPL_HIGH must block everything that can manipulate a run queue.
17 *
18 * The level numbers are picked to fit into APIC vector priorities.
19 *
20 */
21#define IPL_NONE 0x0 /* nothing */
22#define IPL_SOFTCLOCK 0x1 /* timeouts */
23#define IPL_SOFTNET 0x2 /* protocol stacks */
24#define IPL_BIO 0x3 /* block I/O */
25#define IPL_NET 0x4 /* network */
26#define IPL_SOFTTTY 0x8 /* delayed terminal handling */
27#define IPL_TTY 0x9 /* terminal */
28#define IPL_VM 0xa /* memory allocation */
29#define IPL_AUDIO 0xb /* audio */
30#define IPL_CLOCK 0xc /* clock */
31#define IPL_SCHED IPL_CLOCK
32#define IPL_STATCLOCK IPL_CLOCK
33#define IPL_HIGH 0xd /* everything */
34#define IPL_IPI 0xe /* inter-processor interrupts */
35#define NIPL 16
36
37#define IPL_MPFLOOR IPL_TTY
38#define IPL_MPSAFE 0x100
39#define IPL_WAKEUP 0x200
40
41/* Interrupt sharing types. */
42#define IST_NONE 0 /* none */
43#define IST_PULSE 1 /* pulsed */
44#define IST_EDGE 2 /* edge-triggered */
45#define IST_LEVEL 3 /* level-triggered */
46
47/*
48 * Local APIC masks. Must not conflict with SIR_* above, and must
49 * be >= NUM_LEGACY_IRQs. Note that LIR_IPI must be first.
50 */
51#define LIR_IPI 63
52#define LIR_TIMER 62
53
54/* Soft interrupt masks. */
55#define SIR_XCALL 61
56#define SIR_CLOCK 60
57#define SIR_NET 59
58#define SIR_TTY 58
59
60#define LIR_XEN 57
61#define LIR_HYPERV 56
62
63/*
64 * Maximum # of interrupt sources per CPU. 64 to fit in one word.
65 * ioapics can theoretically produce more, but it's not likely to
66 * happen. For multiple ioapics, things can be routed to different
67 * CPUs.
68 */
69#define MAX_INTR_SOURCES 64
70#define NUM_LEGACY_IRQS 16
71
72/*
73 * Low and high boundaries between which interrupt gates will
74 * be allocated in the IDT.
75 */
76#define IDT_INTR_LOW (0x20 + NUM_LEGACY_IRQS)
77#define IDT_INTR_HIGH 0xef
78
79#define X86_IPI_HALT 0x00000001
80#define X86_IPI_NOP 0x00000002
81#define X86_IPI_VMCLEAR_VMM 0x00000004
82#define X86_IPI_PCTR 0x00000010
83#define X86_IPI_MTRR 0x00000020
84#define X86_IPI_SETPERF 0x00000040
85#define X86_IPI_DDB 0x00000080
86#define X86_IPI_START_VMM 0x00000100
87#define X86_IPI_STOP_VMM 0x00000200
88#define X86_IPI_WBINVD 0x00000400
89#define X86_IPI_XCALL 0x00000800
90
91#define X86_NIPI 13
92
93#define IREENT_MAGIC 0x18041969
94
95#endif /* _AMD64_INTRDEFS_H */