1//! This file is auto-generated by tools/update_cpu_features.zig.
2
3const std = @import("../std.zig");
4const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;
6
7pub const Feature = enum {
8 audio,
9 cabac,
10 compound,
11 duplex,
12 hvx,
13 hvx_ieee_fp,
14 hvx_length128b,
15 hvx_length64b,
16 hvx_qfloat,
17 hvxv60,
18 hvxv62,
19 hvxv65,
20 hvxv66,
21 hvxv67,
22 hvxv68,
23 hvxv69,
24 hvxv71,
25 hvxv73,
26 hvxv75,
27 hvxv79,
28 hvxv81,
29 long_calls,
30 mem_noshuf,
31 memops,
32 noreturn_stack_elim,
33 nvj,
34 nvs,
35 packets,
36 prev65,
37 reserved_r19,
38 small_data,
39 tinycore,
40 v5,
41 v55,
42 v60,
43 v62,
44 v65,
45 v66,
46 v67,
47 v68,
48 v69,
49 v71,
50 v73,
51 v75,
52 v79,
53 v81,
54 zreg,
55};
56
57pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
58pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
59pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
60pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
61
62pub const all_features = blk: {
63 const len = @typeInfo(Feature).@"enum".field_names.len;
64 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
65 var result: [len]CpuFeature = undefined;
66 result[@backingInt(Feature.audio)] = .{
67 .llvm_name = "audio",
68 .description = "Hexagon Audio extension instructions",
69 .dependencies = featureSet(&[_]Feature{}),
70 };
71 result[@backingInt(Feature.cabac)] = .{
72 .llvm_name = "cabac",
73 .description = "Emit the CABAC instruction",
74 .dependencies = featureSet(&[_]Feature{}),
75 };
76 result[@backingInt(Feature.compound)] = .{
77 .llvm_name = "compound",
78 .description = "Use compound instructions",
79 .dependencies = featureSet(&[_]Feature{}),
80 };
81 result[@backingInt(Feature.duplex)] = .{
82 .llvm_name = "duplex",
83 .description = "Enable generation of duplex instruction",
84 .dependencies = featureSet(&[_]Feature{}),
85 };
86 result[@backingInt(Feature.hvx)] = .{
87 .llvm_name = "hvx",
88 .description = "Hexagon HVX instructions",
89 .dependencies = featureSet(&[_]Feature{}),
90 };
91 result[@backingInt(Feature.hvx_ieee_fp)] = .{
92 .llvm_name = "hvx-ieee-fp",
93 .description = "Hexagon HVX IEEE floating point instructions",
94 .dependencies = featureSet(&[_]Feature{}),
95 };
96 result[@backingInt(Feature.hvx_length128b)] = .{
97 .llvm_name = "hvx-length128b",
98 .description = "Hexagon HVX 128B instructions",
99 .dependencies = featureSet(&[_]Feature{
100 .hvx,
101 }),
102 };
103 result[@backingInt(Feature.hvx_length64b)] = .{
104 .llvm_name = "hvx-length64b",
105 .description = "Hexagon HVX 64B instructions",
106 .dependencies = featureSet(&[_]Feature{
107 .hvx,
108 }),
109 };
110 result[@backingInt(Feature.hvx_qfloat)] = .{
111 .llvm_name = "hvx-qfloat",
112 .description = "Hexagon HVX QFloating point instructions",
113 .dependencies = featureSet(&[_]Feature{}),
114 };
115 result[@backingInt(Feature.hvxv60)] = .{
116 .llvm_name = "hvxv60",
117 .description = "Hexagon HVX instructions",
118 .dependencies = featureSet(&[_]Feature{
119 .hvx,
120 }),
121 };
122 result[@backingInt(Feature.hvxv62)] = .{
123 .llvm_name = "hvxv62",
124 .description = "Hexagon HVX instructions",
125 .dependencies = featureSet(&[_]Feature{
126 .hvxv60,
127 }),
128 };
129 result[@backingInt(Feature.hvxv65)] = .{
130 .llvm_name = "hvxv65",
131 .description = "Hexagon HVX instructions",
132 .dependencies = featureSet(&[_]Feature{
133 .hvxv62,
134 }),
135 };
136 result[@backingInt(Feature.hvxv66)] = .{
137 .llvm_name = "hvxv66",
138 .description = "Hexagon HVX instructions",
139 .dependencies = featureSet(&[_]Feature{
140 .hvxv65,
141 .zreg,
142 }),
143 };
144 result[@backingInt(Feature.hvxv67)] = .{
145 .llvm_name = "hvxv67",
146 .description = "Hexagon HVX instructions",
147 .dependencies = featureSet(&[_]Feature{
148 .hvxv66,
149 }),
150 };
151 result[@backingInt(Feature.hvxv68)] = .{
152 .llvm_name = "hvxv68",
153 .description = "Hexagon HVX instructions",
154 .dependencies = featureSet(&[_]Feature{
155 .hvxv67,
156 }),
157 };
158 result[@backingInt(Feature.hvxv69)] = .{
159 .llvm_name = "hvxv69",
160 .description = "Hexagon HVX instructions",
161 .dependencies = featureSet(&[_]Feature{
162 .hvxv68,
163 }),
164 };
165 result[@backingInt(Feature.hvxv71)] = .{
166 .llvm_name = "hvxv71",
167 .description = "Hexagon HVX instructions",
168 .dependencies = featureSet(&[_]Feature{
169 .hvxv69,
170 }),
171 };
172 result[@backingInt(Feature.hvxv73)] = .{
173 .llvm_name = "hvxv73",
174 .description = "Hexagon HVX instructions",
175 .dependencies = featureSet(&[_]Feature{
176 .hvxv71,
177 }),
178 };
179 result[@backingInt(Feature.hvxv75)] = .{
180 .llvm_name = "hvxv75",
181 .description = "Hexagon HVX instructions",
182 .dependencies = featureSet(&[_]Feature{
183 .hvxv73,
184 }),
185 };
186 result[@backingInt(Feature.hvxv79)] = .{
187 .llvm_name = "hvxv79",
188 .description = "Hexagon HVX instructions",
189 .dependencies = featureSet(&[_]Feature{
190 .hvxv75,
191 }),
192 };
193 result[@backingInt(Feature.hvxv81)] = .{
194 .llvm_name = "hvxv81",
195 .description = "Hexagon HVX instructions",
196 .dependencies = featureSet(&[_]Feature{
197 .hvxv79,
198 }),
199 };
200 result[@backingInt(Feature.long_calls)] = .{
201 .llvm_name = "long-calls",
202 .description = "Use constant-extended calls",
203 .dependencies = featureSet(&[_]Feature{}),
204 };
205 result[@backingInt(Feature.mem_noshuf)] = .{
206 .llvm_name = "mem_noshuf",
207 .description = "Supports mem_noshuf feature",
208 .dependencies = featureSet(&[_]Feature{}),
209 };
210 result[@backingInt(Feature.memops)] = .{
211 .llvm_name = "memops",
212 .description = "Use memop instructions",
213 .dependencies = featureSet(&[_]Feature{}),
214 };
215 result[@backingInt(Feature.noreturn_stack_elim)] = .{
216 .llvm_name = "noreturn-stack-elim",
217 .description = "Eliminate stack allocation in a noreturn function when possible",
218 .dependencies = featureSet(&[_]Feature{}),
219 };
220 result[@backingInt(Feature.nvj)] = .{
221 .llvm_name = "nvj",
222 .description = "Support for new-value jumps",
223 .dependencies = featureSet(&[_]Feature{
224 .packets,
225 }),
226 };
227 result[@backingInt(Feature.nvs)] = .{
228 .llvm_name = "nvs",
229 .description = "Support for new-value stores",
230 .dependencies = featureSet(&[_]Feature{
231 .packets,
232 }),
233 };
234 result[@backingInt(Feature.packets)] = .{
235 .llvm_name = "packets",
236 .description = "Support for instruction packets",
237 .dependencies = featureSet(&[_]Feature{}),
238 };
239 result[@backingInt(Feature.prev65)] = .{
240 .llvm_name = "prev65",
241 .description = "Support features deprecated in v65",
242 .dependencies = featureSet(&[_]Feature{}),
243 };
244 result[@backingInt(Feature.reserved_r19)] = .{
245 .llvm_name = "reserved-r19",
246 .description = "Reserve register R19",
247 .dependencies = featureSet(&[_]Feature{}),
248 };
249 result[@backingInt(Feature.small_data)] = .{
250 .llvm_name = "small-data",
251 .description = "Allow GP-relative addressing of global variables",
252 .dependencies = featureSet(&[_]Feature{}),
253 };
254 result[@backingInt(Feature.tinycore)] = .{
255 .llvm_name = "tinycore",
256 .description = "Hexagon Tiny Core",
257 .dependencies = featureSet(&[_]Feature{}),
258 };
259 result[@backingInt(Feature.v5)] = .{
260 .llvm_name = "v5",
261 .description = "Enable Hexagon V5 architecture",
262 .dependencies = featureSet(&[_]Feature{}),
263 };
264 result[@backingInt(Feature.v55)] = .{
265 .llvm_name = "v55",
266 .description = "Enable Hexagon V55 architecture",
267 .dependencies = featureSet(&[_]Feature{}),
268 };
269 result[@backingInt(Feature.v60)] = .{
270 .llvm_name = "v60",
271 .description = "Enable Hexagon V60 architecture",
272 .dependencies = featureSet(&[_]Feature{}),
273 };
274 result[@backingInt(Feature.v62)] = .{
275 .llvm_name = "v62",
276 .description = "Enable Hexagon V62 architecture",
277 .dependencies = featureSet(&[_]Feature{}),
278 };
279 result[@backingInt(Feature.v65)] = .{
280 .llvm_name = "v65",
281 .description = "Enable Hexagon V65 architecture",
282 .dependencies = featureSet(&[_]Feature{}),
283 };
284 result[@backingInt(Feature.v66)] = .{
285 .llvm_name = "v66",
286 .description = "Enable Hexagon V66 architecture",
287 .dependencies = featureSet(&[_]Feature{}),
288 };
289 result[@backingInt(Feature.v67)] = .{
290 .llvm_name = "v67",
291 .description = "Enable Hexagon V67 architecture",
292 .dependencies = featureSet(&[_]Feature{}),
293 };
294 result[@backingInt(Feature.v68)] = .{
295 .llvm_name = "v68",
296 .description = "Enable Hexagon V68 architecture",
297 .dependencies = featureSet(&[_]Feature{}),
298 };
299 result[@backingInt(Feature.v69)] = .{
300 .llvm_name = "v69",
301 .description = "Enable Hexagon V69 architecture",
302 .dependencies = featureSet(&[_]Feature{}),
303 };
304 result[@backingInt(Feature.v71)] = .{
305 .llvm_name = "v71",
306 .description = "Enable Hexagon V71 architecture",
307 .dependencies = featureSet(&[_]Feature{}),
308 };
309 result[@backingInt(Feature.v73)] = .{
310 .llvm_name = "v73",
311 .description = "Enable Hexagon V73 architecture",
312 .dependencies = featureSet(&[_]Feature{}),
313 };
314 result[@backingInt(Feature.v75)] = .{
315 .llvm_name = "v75",
316 .description = "Enable Hexagon V75 architecture",
317 .dependencies = featureSet(&[_]Feature{}),
318 };
319 result[@backingInt(Feature.v79)] = .{
320 .llvm_name = "v79",
321 .description = "Enable Hexagon V79 architecture",
322 .dependencies = featureSet(&[_]Feature{}),
323 };
324 result[@backingInt(Feature.v81)] = .{
325 .llvm_name = "v81",
326 .description = "Enable Hexagon V81 architecture",
327 .dependencies = featureSet(&[_]Feature{}),
328 };
329 result[@backingInt(Feature.zreg)] = .{
330 .llvm_name = "zreg",
331 .description = "Hexagon ZReg extension instructions",
332 .dependencies = featureSet(&[_]Feature{}),
333 };
334 const ti = @typeInfo(Feature);
335 for (&result, 0..) |*elem, i| {
336 elem.index = i;
337 elem.name = ti.@"enum".field_names[i];
338 }
339 break :blk result;
340};
341
342pub const cpu = struct {
343 pub const generic: CpuModel = .{
344 .name = "generic",
345 .llvm_name = "generic",
346 .features = featureSet(&[_]Feature{
347 .cabac,
348 .compound,
349 .duplex,
350 .memops,
351 .nvj,
352 .nvs,
353 .prev65,
354 .small_data,
355 .v5,
356 .v55,
357 .v60,
358 }),
359 };
360 pub const hexagonv5: CpuModel = .{
361 .name = "hexagonv5",
362 .llvm_name = "hexagonv5",
363 .features = featureSet(&[_]Feature{
364 .cabac,
365 .compound,
366 .duplex,
367 .memops,
368 .nvj,
369 .nvs,
370 .prev65,
371 .small_data,
372 .v5,
373 }),
374 };
375 pub const hexagonv55: CpuModel = .{
376 .name = "hexagonv55",
377 .llvm_name = "hexagonv55",
378 .features = featureSet(&[_]Feature{
379 .cabac,
380 .compound,
381 .duplex,
382 .memops,
383 .nvj,
384 .nvs,
385 .prev65,
386 .small_data,
387 .v5,
388 .v55,
389 }),
390 };
391 pub const hexagonv60: CpuModel = .{
392 .name = "hexagonv60",
393 .llvm_name = "hexagonv60",
394 .features = featureSet(&[_]Feature{
395 .cabac,
396 .compound,
397 .duplex,
398 .memops,
399 .nvj,
400 .nvs,
401 .prev65,
402 .small_data,
403 .v5,
404 .v55,
405 .v60,
406 }),
407 };
408 pub const hexagonv62: CpuModel = .{
409 .name = "hexagonv62",
410 .llvm_name = "hexagonv62",
411 .features = featureSet(&[_]Feature{
412 .cabac,
413 .compound,
414 .duplex,
415 .memops,
416 .nvj,
417 .nvs,
418 .prev65,
419 .small_data,
420 .v5,
421 .v55,
422 .v60,
423 .v62,
424 }),
425 };
426 pub const hexagonv65: CpuModel = .{
427 .name = "hexagonv65",
428 .llvm_name = "hexagonv65",
429 .features = featureSet(&[_]Feature{
430 .cabac,
431 .compound,
432 .duplex,
433 .mem_noshuf,
434 .memops,
435 .nvj,
436 .nvs,
437 .small_data,
438 .v5,
439 .v55,
440 .v60,
441 .v62,
442 .v65,
443 }),
444 };
445 pub const hexagonv66: CpuModel = .{
446 .name = "hexagonv66",
447 .llvm_name = "hexagonv66",
448 .features = featureSet(&[_]Feature{
449 .cabac,
450 .compound,
451 .duplex,
452 .mem_noshuf,
453 .memops,
454 .nvj,
455 .nvs,
456 .small_data,
457 .v5,
458 .v55,
459 .v60,
460 .v62,
461 .v65,
462 .v66,
463 }),
464 };
465 pub const hexagonv67: CpuModel = .{
466 .name = "hexagonv67",
467 .llvm_name = "hexagonv67",
468 .features = featureSet(&[_]Feature{
469 .cabac,
470 .compound,
471 .duplex,
472 .mem_noshuf,
473 .memops,
474 .nvj,
475 .nvs,
476 .small_data,
477 .v5,
478 .v55,
479 .v60,
480 .v62,
481 .v65,
482 .v66,
483 .v67,
484 }),
485 };
486 pub const hexagonv67t: CpuModel = .{
487 .name = "hexagonv67t",
488 .llvm_name = "hexagonv67t",
489 .features = featureSet(&[_]Feature{
490 .audio,
491 .compound,
492 .mem_noshuf,
493 .memops,
494 .nvs,
495 .small_data,
496 .tinycore,
497 .v5,
498 .v55,
499 .v60,
500 .v62,
501 .v65,
502 .v66,
503 .v67,
504 }),
505 };
506 pub const hexagonv68: CpuModel = .{
507 .name = "hexagonv68",
508 .llvm_name = "hexagonv68",
509 .features = featureSet(&[_]Feature{
510 .cabac,
511 .compound,
512 .duplex,
513 .mem_noshuf,
514 .memops,
515 .nvj,
516 .nvs,
517 .small_data,
518 .v5,
519 .v55,
520 .v60,
521 .v62,
522 .v65,
523 .v66,
524 .v67,
525 .v68,
526 }),
527 };
528 pub const hexagonv69: CpuModel = .{
529 .name = "hexagonv69",
530 .llvm_name = "hexagonv69",
531 .features = featureSet(&[_]Feature{
532 .cabac,
533 .compound,
534 .duplex,
535 .mem_noshuf,
536 .memops,
537 .nvj,
538 .nvs,
539 .small_data,
540 .v5,
541 .v55,
542 .v60,
543 .v62,
544 .v65,
545 .v66,
546 .v67,
547 .v68,
548 .v69,
549 }),
550 };
551 pub const hexagonv71: CpuModel = .{
552 .name = "hexagonv71",
553 .llvm_name = "hexagonv71",
554 .features = featureSet(&[_]Feature{
555 .cabac,
556 .compound,
557 .duplex,
558 .mem_noshuf,
559 .memops,
560 .nvj,
561 .nvs,
562 .small_data,
563 .v5,
564 .v55,
565 .v60,
566 .v62,
567 .v65,
568 .v66,
569 .v67,
570 .v68,
571 .v69,
572 .v71,
573 }),
574 };
575 pub const hexagonv71t: CpuModel = .{
576 .name = "hexagonv71t",
577 .llvm_name = "hexagonv71t",
578 .features = featureSet(&[_]Feature{
579 .audio,
580 .compound,
581 .mem_noshuf,
582 .memops,
583 .nvs,
584 .small_data,
585 .tinycore,
586 .v5,
587 .v55,
588 .v60,
589 .v62,
590 .v65,
591 .v66,
592 .v67,
593 .v68,
594 .v69,
595 .v71,
596 }),
597 };
598 pub const hexagonv73: CpuModel = .{
599 .name = "hexagonv73",
600 .llvm_name = "hexagonv73",
601 .features = featureSet(&[_]Feature{
602 .compound,
603 .duplex,
604 .mem_noshuf,
605 .memops,
606 .nvj,
607 .nvs,
608 .small_data,
609 .v5,
610 .v55,
611 .v60,
612 .v62,
613 .v65,
614 .v66,
615 .v67,
616 .v68,
617 .v69,
618 .v71,
619 .v73,
620 }),
621 };
622 pub const hexagonv75: CpuModel = .{
623 .name = "hexagonv75",
624 .llvm_name = "hexagonv75",
625 .features = featureSet(&[_]Feature{
626 .compound,
627 .duplex,
628 .mem_noshuf,
629 .memops,
630 .nvj,
631 .nvs,
632 .small_data,
633 .v5,
634 .v55,
635 .v60,
636 .v62,
637 .v65,
638 .v66,
639 .v67,
640 .v68,
641 .v69,
642 .v71,
643 .v73,
644 .v75,
645 }),
646 };
647 pub const hexagonv79: CpuModel = .{
648 .name = "hexagonv79",
649 .llvm_name = "hexagonv79",
650 .features = featureSet(&[_]Feature{
651 .compound,
652 .duplex,
653 .mem_noshuf,
654 .memops,
655 .nvj,
656 .nvs,
657 .small_data,
658 .v5,
659 .v55,
660 .v60,
661 .v62,
662 .v65,
663 .v66,
664 .v67,
665 .v68,
666 .v69,
667 .v71,
668 .v73,
669 .v75,
670 .v79,
671 }),
672 };
673 pub const hexagonv81: CpuModel = .{
674 .name = "hexagonv81",
675 .llvm_name = "hexagonv81",
676 .features = featureSet(&[_]Feature{
677 .compound,
678 .duplex,
679 .mem_noshuf,
680 .memops,
681 .nvj,
682 .nvs,
683 .small_data,
684 .v5,
685 .v55,
686 .v60,
687 .v62,
688 .v65,
689 .v66,
690 .v67,
691 .v68,
692 .v69,
693 .v71,
694 .v73,
695 .v75,
696 .v79,
697 .v81,
698 }),
699 };
700};