1//! This file is auto-generated by tools/update_cpu_features.zig.
2
3const std = @import("../std.zig");
4const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;
6
7pub const Feature = enum {
8 abs2008,
9 cnmips,
10 cnmipsp,
11 crc,
12 dsp,
13 dspr2,
14 dspr3,
15 eva,
16 fp64,
17 fpxx,
18 ginv,
19 gp64,
20 i6400,
21 i6500,
22 long_calls,
23 micromips,
24 mips1,
25 mips16,
26 mips2,
27 mips3,
28 mips32,
29 mips32r2,
30 mips32r3,
31 mips32r5,
32 mips32r6,
33 mips3_32,
34 mips3_32r2,
35 mips3d,
36 mips4,
37 mips4_32,
38 mips4_32r2,
39 mips5,
40 mips5_32r2,
41 mips64,
42 mips64r2,
43 mips64r3,
44 mips64r5,
45 mips64r6,
46 msa,
47 mt,
48 nan2008,
49 noabicalls,
50 nomadd4,
51 nooddspreg,
52 notraps,
53 p5600,
54 ptr64,
55 single_float,
56 soft_float,
57 strict_align,
58 sym32,
59 use_compact_branches,
60 use_indirect_jump_hazard,
61 use_tcc_in_div,
62 vfpu,
63 virt,
64 xgot,
65};
66
67pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
68pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
69pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
70pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
71
72pub const all_features = blk: {
73 const len = @typeInfo(Feature).@"enum".field_names.len;
74 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
75 var result: [len]CpuFeature = undefined;
76 result[@backingInt(Feature.abs2008)] = .{
77 .llvm_name = "abs2008",
78 .description = "Disable IEEE 754-2008 abs.fmt mode",
79 .dependencies = featureSet(&[_]Feature{}),
80 };
81 result[@backingInt(Feature.cnmips)] = .{
82 .llvm_name = "cnmips",
83 .description = "Octeon cnMIPS Support",
84 .dependencies = featureSet(&[_]Feature{
85 .mips64r2,
86 }),
87 };
88 result[@backingInt(Feature.cnmipsp)] = .{
89 .llvm_name = "cnmipsp",
90 .description = "Octeon+ cnMIPS Support",
91 .dependencies = featureSet(&[_]Feature{
92 .cnmips,
93 }),
94 };
95 result[@backingInt(Feature.crc)] = .{
96 .llvm_name = "crc",
97 .description = "Mips R6 CRC ASE",
98 .dependencies = featureSet(&[_]Feature{}),
99 };
100 result[@backingInt(Feature.dsp)] = .{
101 .llvm_name = "dsp",
102 .description = "Mips DSP ASE",
103 .dependencies = featureSet(&[_]Feature{}),
104 };
105 result[@backingInt(Feature.dspr2)] = .{
106 .llvm_name = "dspr2",
107 .description = "Mips DSP-R2 ASE",
108 .dependencies = featureSet(&[_]Feature{
109 .dsp,
110 }),
111 };
112 result[@backingInt(Feature.dspr3)] = .{
113 .llvm_name = "dspr3",
114 .description = "Mips DSP-R3 ASE",
115 .dependencies = featureSet(&[_]Feature{
116 .dspr2,
117 }),
118 };
119 result[@backingInt(Feature.eva)] = .{
120 .llvm_name = "eva",
121 .description = "Mips EVA ASE",
122 .dependencies = featureSet(&[_]Feature{}),
123 };
124 result[@backingInt(Feature.fp64)] = .{
125 .llvm_name = "fp64",
126 .description = "Support 64-bit FP registers",
127 .dependencies = featureSet(&[_]Feature{}),
128 };
129 result[@backingInt(Feature.fpxx)] = .{
130 .llvm_name = "fpxx",
131 .description = "Support for FPXX",
132 .dependencies = featureSet(&[_]Feature{}),
133 };
134 result[@backingInt(Feature.ginv)] = .{
135 .llvm_name = "ginv",
136 .description = "Mips Global Invalidate ASE",
137 .dependencies = featureSet(&[_]Feature{}),
138 };
139 result[@backingInt(Feature.gp64)] = .{
140 .llvm_name = "gp64",
141 .description = "General Purpose Registers are 64-bit wide",
142 .dependencies = featureSet(&[_]Feature{}),
143 };
144 result[@backingInt(Feature.i6400)] = .{
145 .llvm_name = "i6400",
146 .description = "MIPS I6400 Processor",
147 .dependencies = featureSet(&[_]Feature{
148 .mips64r6,
149 .msa,
150 }),
151 };
152 result[@backingInt(Feature.i6500)] = .{
153 .llvm_name = "i6500",
154 .description = "MIPS I6500 Processor",
155 .dependencies = featureSet(&[_]Feature{
156 .mips64r6,
157 .msa,
158 }),
159 };
160 result[@backingInt(Feature.long_calls)] = .{
161 .llvm_name = "long-calls",
162 .description = "Disable use of the jal instruction",
163 .dependencies = featureSet(&[_]Feature{}),
164 };
165 result[@backingInt(Feature.micromips)] = .{
166 .llvm_name = "micromips",
167 .description = "microMips mode",
168 .dependencies = featureSet(&[_]Feature{}),
169 };
170 result[@backingInt(Feature.mips1)] = .{
171 .llvm_name = "mips1",
172 .description = "Mips I ISA Support [highly experimental]",
173 .dependencies = featureSet(&[_]Feature{}),
174 };
175 result[@backingInt(Feature.mips16)] = .{
176 .llvm_name = "mips16",
177 .description = "Mips16 mode",
178 .dependencies = featureSet(&[_]Feature{}),
179 };
180 result[@backingInt(Feature.mips2)] = .{
181 .llvm_name = "mips2",
182 .description = "Mips II ISA Support [highly experimental]",
183 .dependencies = featureSet(&[_]Feature{
184 .mips1,
185 }),
186 };
187 result[@backingInt(Feature.mips3)] = .{
188 .llvm_name = "mips3",
189 .description = "MIPS III ISA Support [highly experimental]",
190 .dependencies = featureSet(&[_]Feature{
191 .fp64,
192 .gp64,
193 .mips2,
194 .mips3_32,
195 .mips3_32r2,
196 }),
197 };
198 result[@backingInt(Feature.mips32)] = .{
199 .llvm_name = "mips32",
200 .description = "Mips32 ISA Support",
201 .dependencies = featureSet(&[_]Feature{
202 .mips2,
203 .mips3_32,
204 .mips4_32,
205 }),
206 };
207 result[@backingInt(Feature.mips32r2)] = .{
208 .llvm_name = "mips32r2",
209 .description = "Mips32r2 ISA Support",
210 .dependencies = featureSet(&[_]Feature{
211 .mips32,
212 .mips3_32r2,
213 .mips4_32r2,
214 .mips5_32r2,
215 }),
216 };
217 result[@backingInt(Feature.mips32r3)] = .{
218 .llvm_name = "mips32r3",
219 .description = "Mips32r3 ISA Support",
220 .dependencies = featureSet(&[_]Feature{
221 .mips32r2,
222 }),
223 };
224 result[@backingInt(Feature.mips32r5)] = .{
225 .llvm_name = "mips32r5",
226 .description = "Mips32r5 ISA Support",
227 .dependencies = featureSet(&[_]Feature{
228 .mips32r3,
229 }),
230 };
231 result[@backingInt(Feature.mips32r6)] = .{
232 .llvm_name = "mips32r6",
233 .description = "Mips32r6 ISA Support [experimental]",
234 .dependencies = featureSet(&[_]Feature{
235 .abs2008,
236 .fp64,
237 .mips32r5,
238 .nan2008,
239 }),
240 };
241 result[@backingInt(Feature.mips3_32)] = .{
242 .llvm_name = "mips3_32",
243 .description = "Subset of MIPS-III that is also in MIPS32 [highly experimental]",
244 .dependencies = featureSet(&[_]Feature{}),
245 };
246 result[@backingInt(Feature.mips3_32r2)] = .{
247 .llvm_name = "mips3_32r2",
248 .description = "Subset of MIPS-III that is also in MIPS32r2 [highly experimental]",
249 .dependencies = featureSet(&[_]Feature{}),
250 };
251 result[@backingInt(Feature.mips3d)] = .{
252 .llvm_name = "mips3d",
253 .description = "Mips 3D ASE",
254 .dependencies = featureSet(&[_]Feature{}),
255 };
256 result[@backingInt(Feature.mips4)] = .{
257 .llvm_name = "mips4",
258 .description = "MIPS IV ISA Support",
259 .dependencies = featureSet(&[_]Feature{
260 .mips3,
261 .mips4_32,
262 .mips4_32r2,
263 }),
264 };
265 result[@backingInt(Feature.mips4_32)] = .{
266 .llvm_name = "mips4_32",
267 .description = "Subset of MIPS-IV that is also in MIPS32 [highly experimental]",
268 .dependencies = featureSet(&[_]Feature{}),
269 };
270 result[@backingInt(Feature.mips4_32r2)] = .{
271 .llvm_name = "mips4_32r2",
272 .description = "Subset of MIPS-IV that is also in MIPS32r2 [highly experimental]",
273 .dependencies = featureSet(&[_]Feature{}),
274 };
275 result[@backingInt(Feature.mips5)] = .{
276 .llvm_name = "mips5",
277 .description = "MIPS V ISA Support [highly experimental]",
278 .dependencies = featureSet(&[_]Feature{
279 .mips4,
280 .mips5_32r2,
281 }),
282 };
283 result[@backingInt(Feature.mips5_32r2)] = .{
284 .llvm_name = "mips5_32r2",
285 .description = "Subset of MIPS-V that is also in MIPS32r2 [highly experimental]",
286 .dependencies = featureSet(&[_]Feature{}),
287 };
288 result[@backingInt(Feature.mips64)] = .{
289 .llvm_name = "mips64",
290 .description = "Mips64 ISA Support",
291 .dependencies = featureSet(&[_]Feature{
292 .mips32,
293 .mips5,
294 }),
295 };
296 result[@backingInt(Feature.mips64r2)] = .{
297 .llvm_name = "mips64r2",
298 .description = "Mips64r2 ISA Support",
299 .dependencies = featureSet(&[_]Feature{
300 .mips32r2,
301 .mips64,
302 }),
303 };
304 result[@backingInt(Feature.mips64r3)] = .{
305 .llvm_name = "mips64r3",
306 .description = "Mips64r3 ISA Support",
307 .dependencies = featureSet(&[_]Feature{
308 .mips32r3,
309 .mips64r2,
310 }),
311 };
312 result[@backingInt(Feature.mips64r5)] = .{
313 .llvm_name = "mips64r5",
314 .description = "Mips64r5 ISA Support",
315 .dependencies = featureSet(&[_]Feature{
316 .mips32r5,
317 .mips64r3,
318 }),
319 };
320 result[@backingInt(Feature.mips64r6)] = .{
321 .llvm_name = "mips64r6",
322 .description = "Mips64r6 ISA Support [experimental]",
323 .dependencies = featureSet(&[_]Feature{
324 .mips32r6,
325 .mips64r5,
326 }),
327 };
328 result[@backingInt(Feature.msa)] = .{
329 .llvm_name = "msa",
330 .description = "Mips MSA ASE",
331 .dependencies = featureSet(&[_]Feature{}),
332 };
333 result[@backingInt(Feature.mt)] = .{
334 .llvm_name = "mt",
335 .description = "Mips MT ASE",
336 .dependencies = featureSet(&[_]Feature{}),
337 };
338 result[@backingInt(Feature.nan2008)] = .{
339 .llvm_name = "nan2008",
340 .description = "IEEE 754-2008 NaN encoding",
341 .dependencies = featureSet(&[_]Feature{}),
342 };
343 result[@backingInt(Feature.noabicalls)] = .{
344 .llvm_name = "noabicalls",
345 .description = "Disable SVR4-style position-independent code",
346 .dependencies = featureSet(&[_]Feature{}),
347 };
348 result[@backingInt(Feature.nomadd4)] = .{
349 .llvm_name = "nomadd4",
350 .description = "Disable 4-operand madd.fmt and related instructions",
351 .dependencies = featureSet(&[_]Feature{}),
352 };
353 result[@backingInt(Feature.nooddspreg)] = .{
354 .llvm_name = "nooddspreg",
355 .description = "Disable odd numbered single-precision registers",
356 .dependencies = featureSet(&[_]Feature{}),
357 };
358 result[@backingInt(Feature.notraps)] = .{
359 .llvm_name = null,
360 .description = "Disable trap instructions",
361 .dependencies = featureSet(&[_]Feature{}),
362 };
363 result[@backingInt(Feature.p5600)] = .{
364 .llvm_name = "p5600",
365 .description = "The P5600 Processor",
366 .dependencies = featureSet(&[_]Feature{
367 .mips32r5,
368 }),
369 };
370 result[@backingInt(Feature.ptr64)] = .{
371 .llvm_name = "ptr64",
372 .description = "Pointers are 64-bit wide",
373 .dependencies = featureSet(&[_]Feature{}),
374 };
375 result[@backingInt(Feature.single_float)] = .{
376 .llvm_name = "single-float",
377 .description = "Only supports single precision float",
378 .dependencies = featureSet(&[_]Feature{}),
379 };
380 result[@backingInt(Feature.soft_float)] = .{
381 .llvm_name = "soft-float",
382 .description = "Does not support floating point instructions",
383 .dependencies = featureSet(&[_]Feature{}),
384 };
385 result[@backingInt(Feature.strict_align)] = .{
386 .llvm_name = "strict-align",
387 .description = "Disable unaligned load store for r6",
388 .dependencies = featureSet(&[_]Feature{}),
389 };
390 result[@backingInt(Feature.sym32)] = .{
391 .llvm_name = "sym32",
392 .description = "Symbols are 32 bit on Mips64",
393 .dependencies = featureSet(&[_]Feature{}),
394 };
395 result[@backingInt(Feature.use_compact_branches)] = .{
396 .llvm_name = "use-compact-branches",
397 .description = "Use compact branch instructions for MIPS32R6/MIPS64R6",
398 .dependencies = featureSet(&[_]Feature{}),
399 };
400 result[@backingInt(Feature.use_indirect_jump_hazard)] = .{
401 .llvm_name = "use-indirect-jump-hazard",
402 .description = "Use indirect jump guards to prevent certain speculation based attacks",
403 .dependencies = featureSet(&[_]Feature{}),
404 };
405 result[@backingInt(Feature.use_tcc_in_div)] = .{
406 .llvm_name = "use-tcc-in-div",
407 .description = "Force the assembler to use trapping",
408 .dependencies = featureSet(&[_]Feature{}),
409 };
410 result[@backingInt(Feature.vfpu)] = .{
411 .llvm_name = "vfpu",
412 .description = "Enable vector FPU instructions",
413 .dependencies = featureSet(&[_]Feature{}),
414 };
415 result[@backingInt(Feature.virt)] = .{
416 .llvm_name = "virt",
417 .description = "Mips Virtualization ASE",
418 .dependencies = featureSet(&[_]Feature{}),
419 };
420 result[@backingInt(Feature.xgot)] = .{
421 .llvm_name = "xgot",
422 .description = "Assume 32-bit GOT",
423 .dependencies = featureSet(&[_]Feature{}),
424 };
425 const ti = @typeInfo(Feature);
426 for (&result, 0..) |*elem, i| {
427 elem.index = i;
428 elem.name = ti.@"enum".field_names[i];
429 }
430 break :blk result;
431};
432
433pub const cpu = struct {
434 pub const allegrex: CpuModel = .{
435 .name = "allegrex",
436 .llvm_name = null,
437 .features = featureSet(&[_]Feature{
438 .mips2,
439 .notraps,
440 .single_float,
441 }),
442 };
443 pub const generic: CpuModel = .{
444 .name = "generic",
445 .llvm_name = "generic",
446 .features = featureSet(&[_]Feature{
447 .mips32,
448 }),
449 };
450 pub const @"i6400": CpuModel = .{
451 .name = "i6400",
452 .llvm_name = "i6400",
453 .features = featureSet(&[_]Feature{
454 .i6400,
455 }),
456 };
457 pub const @"i6500": CpuModel = .{
458 .name = "i6500",
459 .llvm_name = "i6500",
460 .features = featureSet(&[_]Feature{
461 .i6500,
462 }),
463 };
464 pub const mips1: CpuModel = .{
465 .name = "mips1",
466 .llvm_name = "mips1",
467 .features = featureSet(&[_]Feature{
468 .mips1,
469 }),
470 };
471 pub const mips2: CpuModel = .{
472 .name = "mips2",
473 .llvm_name = "mips2",
474 .features = featureSet(&[_]Feature{
475 .mips2,
476 }),
477 };
478 pub const mips3: CpuModel = .{
479 .name = "mips3",
480 .llvm_name = "mips3",
481 .features = featureSet(&[_]Feature{
482 .mips3,
483 }),
484 };
485 pub const mips32: CpuModel = .{
486 .name = "mips32",
487 .llvm_name = "mips32",
488 .features = featureSet(&[_]Feature{
489 .mips32,
490 }),
491 };
492 pub const mips32r2: CpuModel = .{
493 .name = "mips32r2",
494 .llvm_name = "mips32r2",
495 .features = featureSet(&[_]Feature{
496 .mips32r2,
497 }),
498 };
499 pub const mips32r3: CpuModel = .{
500 .name = "mips32r3",
501 .llvm_name = "mips32r3",
502 .features = featureSet(&[_]Feature{
503 .mips32r3,
504 }),
505 };
506 pub const mips32r5: CpuModel = .{
507 .name = "mips32r5",
508 .llvm_name = "mips32r5",
509 .features = featureSet(&[_]Feature{
510 .mips32r5,
511 }),
512 };
513 pub const mips32r6: CpuModel = .{
514 .name = "mips32r6",
515 .llvm_name = "mips32r6",
516 .features = featureSet(&[_]Feature{
517 .mips32r6,
518 }),
519 };
520 pub const mips4: CpuModel = .{
521 .name = "mips4",
522 .llvm_name = "mips4",
523 .features = featureSet(&[_]Feature{
524 .mips4,
525 }),
526 };
527 pub const mips5: CpuModel = .{
528 .name = "mips5",
529 .llvm_name = "mips5",
530 .features = featureSet(&[_]Feature{
531 .mips5,
532 }),
533 };
534 pub const mips64: CpuModel = .{
535 .name = "mips64",
536 .llvm_name = "mips64",
537 .features = featureSet(&[_]Feature{
538 .mips64,
539 }),
540 };
541 pub const mips64r2: CpuModel = .{
542 .name = "mips64r2",
543 .llvm_name = "mips64r2",
544 .features = featureSet(&[_]Feature{
545 .mips64r2,
546 }),
547 };
548 pub const mips64r3: CpuModel = .{
549 .name = "mips64r3",
550 .llvm_name = "mips64r3",
551 .features = featureSet(&[_]Feature{
552 .mips64r3,
553 }),
554 };
555 pub const mips64r5: CpuModel = .{
556 .name = "mips64r5",
557 .llvm_name = "mips64r5",
558 .features = featureSet(&[_]Feature{
559 .mips64r5,
560 }),
561 };
562 pub const mips64r6: CpuModel = .{
563 .name = "mips64r6",
564 .llvm_name = "mips64r6",
565 .features = featureSet(&[_]Feature{
566 .mips64r6,
567 }),
568 };
569 pub const octeon: CpuModel = .{
570 .name = "octeon",
571 .llvm_name = "octeon",
572 .features = featureSet(&[_]Feature{
573 .cnmips,
574 }),
575 };
576 pub const @"octeon+": CpuModel = .{
577 .name = "octeon+",
578 .llvm_name = "octeon+",
579 .features = featureSet(&[_]Feature{
580 .cnmipsp,
581 }),
582 };
583 pub const p5600: CpuModel = .{
584 .name = "p5600",
585 .llvm_name = "p5600",
586 .features = featureSet(&[_]Feature{
587 .p5600,
588 }),
589 };
590 pub const r3000a: CpuModel = .{
591 .name = "r3000a",
592 .llvm_name = null,
593 .features = featureSet(&[_]Feature{
594 .mips1,
595 .notraps,
596 .soft_float,
597 }),
598 };
599};