1//! This file is auto-generated by tools/update_cpu_features.zig.
2
3const std = @import("../std.zig");
4const CpuFeature = std.Target.Cpu.Feature;
5const CpuModel = std.Target.Cpu.Model;
6
7pub const Feature = enum {
8 @"64bit",
9 @"64bit_support",
10 @"64bitregs",
11 allow_unaligned_fp_access,
12 altivec,
13 booke,
14 bpermd,
15 cmpb,
16 crbits,
17 crypto,
18 direct_move,
19 e500,
20 efpu2,
21 extdiv,
22 fast_MFLR,
23 fcpsgn,
24 float128,
25 fpcvt,
26 fprnd,
27 fpu,
28 fre,
29 fres,
30 frsqrte,
31 frsqrtes,
32 fsqrt,
33 fuse_add_logical,
34 fuse_addi_load,
35 fuse_addis_load,
36 fuse_arith_add,
37 fuse_back2back,
38 fuse_cmp,
39 fuse_logical,
40 fuse_logical_add,
41 fuse_sha3,
42 fuse_store,
43 fuse_wideimm,
44 fuse_zeromove,
45 fusion,
46 hard_float,
47 htm,
48 icbt,
49 invariant_function_descriptors,
50 isa_future_instructions,
51 isa_v206_instructions,
52 isa_v207_instructions,
53 isa_v30_instructions,
54 isa_v31_instructions,
55 isel,
56 ldbrx,
57 lfiwax,
58 longcall,
59 mfocrf,
60 mma,
61 msync,
62 paired_vector_memops,
63 partword_atomics,
64 pcrelative_memops,
65 popcntd,
66 power10_vector,
67 power8_altivec,
68 power8_vector,
69 power9_altivec,
70 power9_vector,
71 ppc4xx,
72 ppc6xx,
73 ppc_postra_sched,
74 ppc_prera_sched,
75 predictable_select_expensive,
76 prefix_instrs,
77 privileged,
78 quadword_atomics,
79 recipprec,
80 rop_protect,
81 secure_plt,
82 slow_popcntd,
83 spe,
84 stfiwx,
85 two_const_nr,
86 vectors_use_two_units,
87 vsx,
88};
89
90pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
91pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
92pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
93pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
94
95pub const all_features = blk: {
96 const len = @typeInfo(Feature).@"enum".field_names.len;
97 std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
98 var result: [len]CpuFeature = undefined;
99 result[@backingInt(Feature.@"64bit")] = .{
100 .llvm_name = "64bit",
101 .description = "Enable 64-bit mode",
102 .dependencies = featureSet(&[_]Feature{
103 .@"64bit_support",
104 }),
105 };
106 result[@backingInt(Feature.@"64bit_support")] = .{
107 .llvm_name = "64bit-support",
108 .description = "Supports 64-bit instructions",
109 .dependencies = featureSet(&[_]Feature{}),
110 };
111 result[@backingInt(Feature.@"64bitregs")] = .{
112 .llvm_name = "64bitregs",
113 .description = "Enable 64-bit registers usage for ppc32 [beta]",
114 .dependencies = featureSet(&[_]Feature{}),
115 };
116 result[@backingInt(Feature.allow_unaligned_fp_access)] = .{
117 .llvm_name = "allow-unaligned-fp-access",
118 .description = "CPU does not trap on unaligned FP access",
119 .dependencies = featureSet(&[_]Feature{}),
120 };
121 result[@backingInt(Feature.altivec)] = .{
122 .llvm_name = "altivec",
123 .description = "Enable Altivec instructions",
124 .dependencies = featureSet(&[_]Feature{
125 .fpu,
126 }),
127 };
128 result[@backingInt(Feature.booke)] = .{
129 .llvm_name = "booke",
130 .description = "Enable Book E instructions",
131 .dependencies = featureSet(&[_]Feature{
132 .icbt,
133 }),
134 };
135 result[@backingInt(Feature.bpermd)] = .{
136 .llvm_name = "bpermd",
137 .description = "Enable the bpermd instruction",
138 .dependencies = featureSet(&[_]Feature{}),
139 };
140 result[@backingInt(Feature.cmpb)] = .{
141 .llvm_name = "cmpb",
142 .description = "Enable the cmpb instruction",
143 .dependencies = featureSet(&[_]Feature{}),
144 };
145 result[@backingInt(Feature.crbits)] = .{
146 .llvm_name = "crbits",
147 .description = "Use condition-register bits individually",
148 .dependencies = featureSet(&[_]Feature{}),
149 };
150 result[@backingInt(Feature.crypto)] = .{
151 .llvm_name = "crypto",
152 .description = "Enable POWER8 Crypto instructions",
153 .dependencies = featureSet(&[_]Feature{
154 .power8_altivec,
155 }),
156 };
157 result[@backingInt(Feature.direct_move)] = .{
158 .llvm_name = "direct-move",
159 .description = "Enable Power8 direct move instructions",
160 .dependencies = featureSet(&[_]Feature{
161 .vsx,
162 }),
163 };
164 result[@backingInt(Feature.e500)] = .{
165 .llvm_name = "e500",
166 .description = "Enable E500/E500mc instructions",
167 .dependencies = featureSet(&[_]Feature{}),
168 };
169 result[@backingInt(Feature.efpu2)] = .{
170 .llvm_name = "efpu2",
171 .description = "Enable Embedded Floating-Point APU 2 instructions",
172 .dependencies = featureSet(&[_]Feature{
173 .spe,
174 }),
175 };
176 result[@backingInt(Feature.extdiv)] = .{
177 .llvm_name = "extdiv",
178 .description = "Enable extended divide instructions",
179 .dependencies = featureSet(&[_]Feature{}),
180 };
181 result[@backingInt(Feature.fast_MFLR)] = .{
182 .llvm_name = "fast-MFLR",
183 .description = "MFLR is a fast instruction",
184 .dependencies = featureSet(&[_]Feature{}),
185 };
186 result[@backingInt(Feature.fcpsgn)] = .{
187 .llvm_name = "fcpsgn",
188 .description = "Enable the fcpsgn instruction",
189 .dependencies = featureSet(&[_]Feature{
190 .fpu,
191 }),
192 };
193 result[@backingInt(Feature.float128)] = .{
194 .llvm_name = "float128",
195 .description = "Enable the __float128 data type for IEEE-754R Binary128.",
196 .dependencies = featureSet(&[_]Feature{
197 .vsx,
198 }),
199 };
200 result[@backingInt(Feature.fpcvt)] = .{
201 .llvm_name = "fpcvt",
202 .description = "Enable fc[ft]* (unsigned and single-precision) and lfiwzx instructions",
203 .dependencies = featureSet(&[_]Feature{
204 .fpu,
205 }),
206 };
207 result[@backingInt(Feature.fprnd)] = .{
208 .llvm_name = "fprnd",
209 .description = "Enable the fri[mnpz] instructions",
210 .dependencies = featureSet(&[_]Feature{
211 .fpu,
212 }),
213 };
214 result[@backingInt(Feature.fpu)] = .{
215 .llvm_name = "fpu",
216 .description = "Enable classic FPU instructions",
217 .dependencies = featureSet(&[_]Feature{
218 .hard_float,
219 }),
220 };
221 result[@backingInt(Feature.fre)] = .{
222 .llvm_name = "fre",
223 .description = "Enable the fre instruction",
224 .dependencies = featureSet(&[_]Feature{
225 .fpu,
226 }),
227 };
228 result[@backingInt(Feature.fres)] = .{
229 .llvm_name = "fres",
230 .description = "Enable the fres instruction",
231 .dependencies = featureSet(&[_]Feature{
232 .fpu,
233 }),
234 };
235 result[@backingInt(Feature.frsqrte)] = .{
236 .llvm_name = "frsqrte",
237 .description = "Enable the frsqrte instruction",
238 .dependencies = featureSet(&[_]Feature{
239 .fpu,
240 }),
241 };
242 result[@backingInt(Feature.frsqrtes)] = .{
243 .llvm_name = "frsqrtes",
244 .description = "Enable the frsqrtes instruction",
245 .dependencies = featureSet(&[_]Feature{
246 .fpu,
247 }),
248 };
249 result[@backingInt(Feature.fsqrt)] = .{
250 .llvm_name = "fsqrt",
251 .description = "Enable the fsqrt instruction",
252 .dependencies = featureSet(&[_]Feature{
253 .fpu,
254 }),
255 };
256 result[@backingInt(Feature.fuse_add_logical)] = .{
257 .llvm_name = "fuse-add-logical",
258 .description = "Target supports Add with Logical Operations fusion",
259 .dependencies = featureSet(&[_]Feature{
260 .fusion,
261 }),
262 };
263 result[@backingInt(Feature.fuse_addi_load)] = .{
264 .llvm_name = "fuse-addi-load",
265 .description = "Power8 Addi-Load fusion",
266 .dependencies = featureSet(&[_]Feature{
267 .fusion,
268 }),
269 };
270 result[@backingInt(Feature.fuse_addis_load)] = .{
271 .llvm_name = "fuse-addis-load",
272 .description = "Power8 Addis-Load fusion",
273 .dependencies = featureSet(&[_]Feature{
274 .fusion,
275 }),
276 };
277 result[@backingInt(Feature.fuse_arith_add)] = .{
278 .llvm_name = "fuse-arith-add",
279 .description = "Target supports Arithmetic Operations with Add fusion",
280 .dependencies = featureSet(&[_]Feature{
281 .fusion,
282 }),
283 };
284 result[@backingInt(Feature.fuse_back2back)] = .{
285 .llvm_name = "fuse-back2back",
286 .description = "Target supports general back to back fusion",
287 .dependencies = featureSet(&[_]Feature{
288 .fusion,
289 }),
290 };
291 result[@backingInt(Feature.fuse_cmp)] = .{
292 .llvm_name = "fuse-cmp",
293 .description = "Target supports Comparison Operations fusion",
294 .dependencies = featureSet(&[_]Feature{
295 .fusion,
296 }),
297 };
298 result[@backingInt(Feature.fuse_logical)] = .{
299 .llvm_name = "fuse-logical",
300 .description = "Target supports Logical Operations fusion",
301 .dependencies = featureSet(&[_]Feature{
302 .fusion,
303 }),
304 };
305 result[@backingInt(Feature.fuse_logical_add)] = .{
306 .llvm_name = "fuse-logical-add",
307 .description = "Target supports Logical with Add Operations fusion",
308 .dependencies = featureSet(&[_]Feature{
309 .fusion,
310 }),
311 };
312 result[@backingInt(Feature.fuse_sha3)] = .{
313 .llvm_name = "fuse-sha3",
314 .description = "Target supports SHA3 assist fusion",
315 .dependencies = featureSet(&[_]Feature{
316 .fusion,
317 }),
318 };
319 result[@backingInt(Feature.fuse_store)] = .{
320 .llvm_name = "fuse-store",
321 .description = "Target supports store clustering",
322 .dependencies = featureSet(&[_]Feature{
323 .fusion,
324 }),
325 };
326 result[@backingInt(Feature.fuse_wideimm)] = .{
327 .llvm_name = "fuse-wideimm",
328 .description = "Target supports Wide-Immediate fusion",
329 .dependencies = featureSet(&[_]Feature{
330 .fusion,
331 }),
332 };
333 result[@backingInt(Feature.fuse_zeromove)] = .{
334 .llvm_name = "fuse-zeromove",
335 .description = "Target supports move to SPR with branch fusion",
336 .dependencies = featureSet(&[_]Feature{
337 .fusion,
338 }),
339 };
340 result[@backingInt(Feature.fusion)] = .{
341 .llvm_name = "fusion",
342 .description = "Target supports instruction fusion",
343 .dependencies = featureSet(&[_]Feature{}),
344 };
345 result[@backingInt(Feature.hard_float)] = .{
346 .llvm_name = "hard-float",
347 .description = "Enable floating-point instructions",
348 .dependencies = featureSet(&[_]Feature{}),
349 };
350 result[@backingInt(Feature.htm)] = .{
351 .llvm_name = "htm",
352 .description = "Enable Hardware Transactional Memory instructions",
353 .dependencies = featureSet(&[_]Feature{}),
354 };
355 result[@backingInt(Feature.icbt)] = .{
356 .llvm_name = "icbt",
357 .description = "Enable icbt instruction",
358 .dependencies = featureSet(&[_]Feature{}),
359 };
360 result[@backingInt(Feature.invariant_function_descriptors)] = .{
361 .llvm_name = "invariant-function-descriptors",
362 .description = "Assume function descriptors are invariant",
363 .dependencies = featureSet(&[_]Feature{}),
364 };
365 result[@backingInt(Feature.isa_future_instructions)] = .{
366 .llvm_name = "isa-future-instructions",
367 .description = "Enable instructions for Future ISA.",
368 .dependencies = featureSet(&[_]Feature{
369 .isa_v31_instructions,
370 }),
371 };
372 result[@backingInt(Feature.isa_v206_instructions)] = .{
373 .llvm_name = "isa-v206-instructions",
374 .description = "Enable instructions in ISA 2.06.",
375 .dependencies = featureSet(&[_]Feature{}),
376 };
377 result[@backingInt(Feature.isa_v207_instructions)] = .{
378 .llvm_name = "isa-v207-instructions",
379 .description = "Enable instructions in ISA 2.07.",
380 .dependencies = featureSet(&[_]Feature{}),
381 };
382 result[@backingInt(Feature.isa_v30_instructions)] = .{
383 .llvm_name = "isa-v30-instructions",
384 .description = "Enable instructions in ISA 3.0.",
385 .dependencies = featureSet(&[_]Feature{
386 .isa_v207_instructions,
387 }),
388 };
389 result[@backingInt(Feature.isa_v31_instructions)] = .{
390 .llvm_name = "isa-v31-instructions",
391 .description = "Enable instructions in ISA 3.1.",
392 .dependencies = featureSet(&[_]Feature{
393 .isa_v30_instructions,
394 }),
395 };
396 result[@backingInt(Feature.isel)] = .{
397 .llvm_name = "isel",
398 .description = "Enable the isel instruction",
399 .dependencies = featureSet(&[_]Feature{}),
400 };
401 result[@backingInt(Feature.ldbrx)] = .{
402 .llvm_name = "ldbrx",
403 .description = "Enable the ldbrx instruction",
404 .dependencies = featureSet(&[_]Feature{}),
405 };
406 result[@backingInt(Feature.lfiwax)] = .{
407 .llvm_name = "lfiwax",
408 .description = "Enable the lfiwax instruction",
409 .dependencies = featureSet(&[_]Feature{
410 .fpu,
411 }),
412 };
413 result[@backingInt(Feature.longcall)] = .{
414 .llvm_name = "longcall",
415 .description = "Always use indirect calls",
416 .dependencies = featureSet(&[_]Feature{}),
417 };
418 result[@backingInt(Feature.mfocrf)] = .{
419 .llvm_name = "mfocrf",
420 .description = "Enable the MFOCRF instruction",
421 .dependencies = featureSet(&[_]Feature{}),
422 };
423 result[@backingInt(Feature.mma)] = .{
424 .llvm_name = "mma",
425 .description = "Enable MMA instructions",
426 .dependencies = featureSet(&[_]Feature{
427 .paired_vector_memops,
428 .power8_vector,
429 .power9_altivec,
430 }),
431 };
432 result[@backingInt(Feature.msync)] = .{
433 .llvm_name = "msync",
434 .description = "Has only the msync instruction instead of sync",
435 .dependencies = featureSet(&[_]Feature{
436 .booke,
437 }),
438 };
439 result[@backingInt(Feature.paired_vector_memops)] = .{
440 .llvm_name = "paired-vector-memops",
441 .description = "32Byte load and store instructions",
442 .dependencies = featureSet(&[_]Feature{
443 .isa_v30_instructions,
444 }),
445 };
446 result[@backingInt(Feature.partword_atomics)] = .{
447 .llvm_name = "partword-atomics",
448 .description = "Enable l[bh]arx and st[bh]cx.",
449 .dependencies = featureSet(&[_]Feature{}),
450 };
451 result[@backingInt(Feature.pcrelative_memops)] = .{
452 .llvm_name = "pcrelative-memops",
453 .description = "Enable PC relative Memory Ops",
454 .dependencies = featureSet(&[_]Feature{
455 .prefix_instrs,
456 }),
457 };
458 result[@backingInt(Feature.popcntd)] = .{
459 .llvm_name = "popcntd",
460 .description = "Enable the popcnt[dw] instructions",
461 .dependencies = featureSet(&[_]Feature{}),
462 };
463 result[@backingInt(Feature.power10_vector)] = .{
464 .llvm_name = "power10-vector",
465 .description = "Enable POWER10 vector instructions",
466 .dependencies = featureSet(&[_]Feature{
467 .isa_v31_instructions,
468 .power9_vector,
469 }),
470 };
471 result[@backingInt(Feature.power8_altivec)] = .{
472 .llvm_name = "power8-altivec",
473 .description = "Enable POWER8 Altivec instructions",
474 .dependencies = featureSet(&[_]Feature{
475 .altivec,
476 }),
477 };
478 result[@backingInt(Feature.power8_vector)] = .{
479 .llvm_name = "power8-vector",
480 .description = "Enable POWER8 vector instructions",
481 .dependencies = featureSet(&[_]Feature{
482 .power8_altivec,
483 .vsx,
484 }),
485 };
486 result[@backingInt(Feature.power9_altivec)] = .{
487 .llvm_name = "power9-altivec",
488 .description = "Enable POWER9 Altivec instructions",
489 .dependencies = featureSet(&[_]Feature{
490 .isa_v30_instructions,
491 .power8_altivec,
492 }),
493 };
494 result[@backingInt(Feature.power9_vector)] = .{
495 .llvm_name = "power9-vector",
496 .description = "Enable POWER9 vector instructions",
497 .dependencies = featureSet(&[_]Feature{
498 .power8_vector,
499 .power9_altivec,
500 }),
501 };
502 result[@backingInt(Feature.ppc4xx)] = .{
503 .llvm_name = "ppc4xx",
504 .description = "Enable PPC 4xx instructions",
505 .dependencies = featureSet(&[_]Feature{}),
506 };
507 result[@backingInt(Feature.ppc6xx)] = .{
508 .llvm_name = "ppc6xx",
509 .description = "Enable PPC 6xx instructions",
510 .dependencies = featureSet(&[_]Feature{}),
511 };
512 result[@backingInt(Feature.ppc_postra_sched)] = .{
513 .llvm_name = "ppc-postra-sched",
514 .description = "Use PowerPC post-RA scheduling strategy",
515 .dependencies = featureSet(&[_]Feature{}),
516 };
517 result[@backingInt(Feature.ppc_prera_sched)] = .{
518 .llvm_name = "ppc-prera-sched",
519 .description = "Use PowerPC pre-RA scheduling strategy",
520 .dependencies = featureSet(&[_]Feature{}),
521 };
522 result[@backingInt(Feature.predictable_select_expensive)] = .{
523 .llvm_name = "predictable-select-expensive",
524 .description = "Prefer likely predicted branches over selects",
525 .dependencies = featureSet(&[_]Feature{}),
526 };
527 result[@backingInt(Feature.prefix_instrs)] = .{
528 .llvm_name = "prefix-instrs",
529 .description = "Enable prefixed instructions",
530 .dependencies = featureSet(&[_]Feature{
531 .isa_v31_instructions,
532 }),
533 };
534 result[@backingInt(Feature.privileged)] = .{
535 .llvm_name = "privileged",
536 .description = "Add privileged instructions",
537 .dependencies = featureSet(&[_]Feature{}),
538 };
539 result[@backingInt(Feature.quadword_atomics)] = .{
540 .llvm_name = "quadword-atomics",
541 .description = "Enable lqarx and stqcx.",
542 .dependencies = featureSet(&[_]Feature{}),
543 };
544 result[@backingInt(Feature.recipprec)] = .{
545 .llvm_name = "recipprec",
546 .description = "Assume higher precision reciprocal estimates",
547 .dependencies = featureSet(&[_]Feature{}),
548 };
549 result[@backingInt(Feature.rop_protect)] = .{
550 .llvm_name = "rop-protect",
551 .description = "Add ROP protect",
552 .dependencies = featureSet(&[_]Feature{}),
553 };
554 result[@backingInt(Feature.secure_plt)] = .{
555 .llvm_name = "secure-plt",
556 .description = "Enable secure plt mode",
557 .dependencies = featureSet(&[_]Feature{}),
558 };
559 result[@backingInt(Feature.slow_popcntd)] = .{
560 .llvm_name = "slow-popcntd",
561 .description = "Has slow popcnt[dw] instructions",
562 .dependencies = featureSet(&[_]Feature{}),
563 };
564 result[@backingInt(Feature.spe)] = .{
565 .llvm_name = "spe",
566 .description = "Enable SPE instructions",
567 .dependencies = featureSet(&[_]Feature{
568 .hard_float,
569 }),
570 };
571 result[@backingInt(Feature.stfiwx)] = .{
572 .llvm_name = "stfiwx",
573 .description = "Enable the stfiwx instruction",
574 .dependencies = featureSet(&[_]Feature{
575 .fpu,
576 }),
577 };
578 result[@backingInt(Feature.two_const_nr)] = .{
579 .llvm_name = "two-const-nr",
580 .description = "Requires two constant Newton-Raphson computation",
581 .dependencies = featureSet(&[_]Feature{}),
582 };
583 result[@backingInt(Feature.vectors_use_two_units)] = .{
584 .llvm_name = "vectors-use-two-units",
585 .description = "Vectors use two units",
586 .dependencies = featureSet(&[_]Feature{}),
587 };
588 result[@backingInt(Feature.vsx)] = .{
589 .llvm_name = "vsx",
590 .description = "Enable VSX instructions",
591 .dependencies = featureSet(&[_]Feature{
592 .altivec,
593 }),
594 };
595 const ti = @typeInfo(Feature);
596 for (&result, 0..) |*elem, i| {
597 elem.index = i;
598 elem.name = ti.@"enum".field_names[i];
599 }
600 break :blk result;
601};
602
603pub const cpu = struct {
604 pub const @"440": CpuModel = .{
605 .name = "440",
606 .llvm_name = "440",
607 .features = featureSet(&[_]Feature{
608 .fres,
609 .frsqrte,
610 .isel,
611 .msync,
612 }),
613 };
614 pub const @"450": CpuModel = .{
615 .name = "450",
616 .llvm_name = "450",
617 .features = featureSet(&[_]Feature{
618 .fres,
619 .frsqrte,
620 .isel,
621 .msync,
622 }),
623 };
624 pub const @"601": CpuModel = .{
625 .name = "601",
626 .llvm_name = "601",
627 .features = featureSet(&[_]Feature{
628 .fpu,
629 }),
630 };
631 pub const @"602": CpuModel = .{
632 .name = "602",
633 .llvm_name = "602",
634 .features = featureSet(&[_]Feature{
635 .fpu,
636 }),
637 };
638 pub const @"603": CpuModel = .{
639 .name = "603",
640 .llvm_name = "603",
641 .features = featureSet(&[_]Feature{
642 .fres,
643 .frsqrte,
644 }),
645 };
646 pub const @"603e": CpuModel = .{
647 .name = "603e",
648 .llvm_name = "603e",
649 .features = featureSet(&[_]Feature{
650 .fres,
651 .frsqrte,
652 }),
653 };
654 pub const @"603ev": CpuModel = .{
655 .name = "603ev",
656 .llvm_name = "603ev",
657 .features = featureSet(&[_]Feature{
658 .fres,
659 .frsqrte,
660 }),
661 };
662 pub const @"604": CpuModel = .{
663 .name = "604",
664 .llvm_name = "604",
665 .features = featureSet(&[_]Feature{
666 .fres,
667 .frsqrte,
668 }),
669 };
670 pub const @"604e": CpuModel = .{
671 .name = "604e",
672 .llvm_name = "604e",
673 .features = featureSet(&[_]Feature{
674 .fres,
675 .frsqrte,
676 }),
677 };
678 pub const @"620": CpuModel = .{
679 .name = "620",
680 .llvm_name = "620",
681 .features = featureSet(&[_]Feature{
682 .fres,
683 .frsqrte,
684 }),
685 };
686 pub const @"7400": CpuModel = .{
687 .name = "7400",
688 .llvm_name = "7400",
689 .features = featureSet(&[_]Feature{
690 .altivec,
691 .fres,
692 .frsqrte,
693 }),
694 };
695 pub const @"7450": CpuModel = .{
696 .name = "7450",
697 .llvm_name = "7450",
698 .features = featureSet(&[_]Feature{
699 .altivec,
700 .fres,
701 .frsqrte,
702 }),
703 };
704 pub const @"750": CpuModel = .{
705 .name = "750",
706 .llvm_name = "750",
707 .features = featureSet(&[_]Feature{
708 .fres,
709 .frsqrte,
710 }),
711 };
712 pub const @"970": CpuModel = .{
713 .name = "970",
714 .llvm_name = "970",
715 .features = featureSet(&[_]Feature{
716 .@"64bit_support",
717 .altivec,
718 .fres,
719 .frsqrte,
720 .fsqrt,
721 .mfocrf,
722 .stfiwx,
723 }),
724 };
725 pub const a2: CpuModel = .{
726 .name = "a2",
727 .llvm_name = "a2",
728 .features = featureSet(&[_]Feature{
729 .@"64bit_support",
730 .booke,
731 .cmpb,
732 .fcpsgn,
733 .fpcvt,
734 .fprnd,
735 .fre,
736 .fres,
737 .frsqrte,
738 .frsqrtes,
739 .fsqrt,
740 .isa_v206_instructions,
741 .isel,
742 .ldbrx,
743 .lfiwax,
744 .mfocrf,
745 .recipprec,
746 .slow_popcntd,
747 .stfiwx,
748 }),
749 };
750 pub const e500: CpuModel = .{
751 .name = "e500",
752 .llvm_name = "e500",
753 .features = featureSet(&[_]Feature{
754 .isel,
755 .msync,
756 .spe,
757 }),
758 };
759 pub const e500mc: CpuModel = .{
760 .name = "e500mc",
761 .llvm_name = "e500mc",
762 .features = featureSet(&[_]Feature{
763 .booke,
764 .isel,
765 .stfiwx,
766 }),
767 };
768 pub const e5500: CpuModel = .{
769 .name = "e5500",
770 .llvm_name = "e5500",
771 .features = featureSet(&[_]Feature{
772 .@"64bit_support",
773 .booke,
774 .isel,
775 .mfocrf,
776 .stfiwx,
777 }),
778 };
779 pub const future: CpuModel = .{
780 .name = "future",
781 .llvm_name = "future",
782 .features = featureSet(&[_]Feature{
783 .@"64bit_support",
784 .allow_unaligned_fp_access,
785 .bpermd,
786 .cmpb,
787 .crbits,
788 .crypto,
789 .direct_move,
790 .extdiv,
791 .fast_MFLR,
792 .fcpsgn,
793 .fpcvt,
794 .fprnd,
795 .fre,
796 .fres,
797 .frsqrte,
798 .frsqrtes,
799 .fsqrt,
800 .fuse_add_logical,
801 .fuse_arith_add,
802 .fuse_logical,
803 .fuse_logical_add,
804 .fuse_sha3,
805 .fuse_store,
806 .icbt,
807 .isa_future_instructions,
808 .isa_v206_instructions,
809 .isel,
810 .ldbrx,
811 .lfiwax,
812 .mfocrf,
813 .mma,
814 .partword_atomics,
815 .pcrelative_memops,
816 .popcntd,
817 .power10_vector,
818 .ppc_postra_sched,
819 .ppc_prera_sched,
820 .predictable_select_expensive,
821 .quadword_atomics,
822 .recipprec,
823 .stfiwx,
824 .two_const_nr,
825 }),
826 };
827 pub const g3: CpuModel = .{
828 .name = "g3",
829 .llvm_name = "g3",
830 .features = featureSet(&[_]Feature{
831 .fres,
832 .frsqrte,
833 }),
834 };
835 pub const g4: CpuModel = .{
836 .name = "g4",
837 .llvm_name = "g4",
838 .features = featureSet(&[_]Feature{
839 .altivec,
840 .fres,
841 .frsqrte,
842 }),
843 };
844 pub const @"g4+": CpuModel = .{
845 .name = "g4+",
846 .llvm_name = "g4+",
847 .features = featureSet(&[_]Feature{
848 .altivec,
849 .fres,
850 .frsqrte,
851 }),
852 };
853 pub const g5: CpuModel = .{
854 .name = "g5",
855 .llvm_name = "g5",
856 .features = featureSet(&[_]Feature{
857 .@"64bit_support",
858 .altivec,
859 .fres,
860 .frsqrte,
861 .fsqrt,
862 .mfocrf,
863 .stfiwx,
864 }),
865 };
866 pub const generic: CpuModel = .{
867 .name = "generic",
868 .llvm_name = "generic",
869 .features = featureSet(&[_]Feature{
870 .hard_float,
871 }),
872 };
873 pub const ppc: CpuModel = .{
874 .name = "ppc",
875 .llvm_name = "ppc",
876 .features = featureSet(&[_]Feature{
877 .hard_float,
878 }),
879 };
880 pub const ppc64: CpuModel = .{
881 .name = "ppc64",
882 .llvm_name = "ppc64",
883 .features = featureSet(&[_]Feature{
884 .@"64bit_support",
885 .altivec,
886 .fres,
887 .frsqrte,
888 .fsqrt,
889 .mfocrf,
890 .stfiwx,
891 }),
892 };
893 pub const ppc64le: CpuModel = .{
894 .name = "ppc64le",
895 .llvm_name = "ppc64le",
896 .features = featureSet(&[_]Feature{
897 .@"64bit_support",
898 .allow_unaligned_fp_access,
899 .bpermd,
900 .cmpb,
901 .crbits,
902 .crypto,
903 .direct_move,
904 .extdiv,
905 .fcpsgn,
906 .fpcvt,
907 .fprnd,
908 .fre,
909 .fres,
910 .frsqrte,
911 .frsqrtes,
912 .fsqrt,
913 .fuse_addi_load,
914 .fuse_addis_load,
915 .htm,
916 .icbt,
917 .isa_v206_instructions,
918 .isa_v207_instructions,
919 .isel,
920 .ldbrx,
921 .lfiwax,
922 .mfocrf,
923 .partword_atomics,
924 .popcntd,
925 .power8_vector,
926 .predictable_select_expensive,
927 .quadword_atomics,
928 .recipprec,
929 .stfiwx,
930 .two_const_nr,
931 }),
932 };
933 pub const pwr10: CpuModel = .{
934 .name = "pwr10",
935 .llvm_name = "pwr10",
936 .features = featureSet(&[_]Feature{
937 .@"64bit_support",
938 .allow_unaligned_fp_access,
939 .bpermd,
940 .cmpb,
941 .crbits,
942 .crypto,
943 .direct_move,
944 .extdiv,
945 .fast_MFLR,
946 .fcpsgn,
947 .fpcvt,
948 .fprnd,
949 .fre,
950 .fres,
951 .frsqrte,
952 .frsqrtes,
953 .fsqrt,
954 .fuse_add_logical,
955 .fuse_arith_add,
956 .fuse_logical,
957 .fuse_logical_add,
958 .fuse_sha3,
959 .fuse_store,
960 .icbt,
961 .isa_v206_instructions,
962 .isel,
963 .ldbrx,
964 .lfiwax,
965 .mfocrf,
966 .mma,
967 .partword_atomics,
968 .pcrelative_memops,
969 .popcntd,
970 .power10_vector,
971 .ppc_postra_sched,
972 .ppc_prera_sched,
973 .predictable_select_expensive,
974 .quadword_atomics,
975 .recipprec,
976 .stfiwx,
977 .two_const_nr,
978 }),
979 };
980 pub const pwr11: CpuModel = .{
981 .name = "pwr11",
982 .llvm_name = "pwr11",
983 .features = featureSet(&[_]Feature{
984 .@"64bit_support",
985 .allow_unaligned_fp_access,
986 .bpermd,
987 .cmpb,
988 .crbits,
989 .crypto,
990 .direct_move,
991 .extdiv,
992 .fast_MFLR,
993 .fcpsgn,
994 .fpcvt,
995 .fprnd,
996 .fre,
997 .fres,
998 .frsqrte,
999 .frsqrtes,
1000 .fsqrt,
1001 .fuse_add_logical,
1002 .fuse_arith_add,
1003 .fuse_logical,
1004 .fuse_logical_add,
1005 .fuse_sha3,
1006 .fuse_store,
1007 .icbt,
1008 .isa_v206_instructions,
1009 .isel,
1010 .ldbrx,
1011 .lfiwax,
1012 .mfocrf,
1013 .mma,
1014 .partword_atomics,
1015 .pcrelative_memops,
1016 .popcntd,
1017 .power10_vector,
1018 .ppc_postra_sched,
1019 .ppc_prera_sched,
1020 .predictable_select_expensive,
1021 .quadword_atomics,
1022 .recipprec,
1023 .stfiwx,
1024 .two_const_nr,
1025 }),
1026 };
1027 pub const pwr3: CpuModel = .{
1028 .name = "pwr3",
1029 .llvm_name = "pwr3",
1030 .features = featureSet(&[_]Feature{
1031 .@"64bit_support",
1032 .altivec,
1033 .fres,
1034 .frsqrte,
1035 .mfocrf,
1036 .stfiwx,
1037 }),
1038 };
1039 pub const pwr4: CpuModel = .{
1040 .name = "pwr4",
1041 .llvm_name = "pwr4",
1042 .features = featureSet(&[_]Feature{
1043 .@"64bit_support",
1044 .altivec,
1045 .fres,
1046 .frsqrte,
1047 .fsqrt,
1048 .mfocrf,
1049 .stfiwx,
1050 }),
1051 };
1052 pub const pwr5: CpuModel = .{
1053 .name = "pwr5",
1054 .llvm_name = "pwr5",
1055 .features = featureSet(&[_]Feature{
1056 .@"64bit_support",
1057 .altivec,
1058 .fre,
1059 .fres,
1060 .frsqrte,
1061 .frsqrtes,
1062 .fsqrt,
1063 .mfocrf,
1064 .stfiwx,
1065 }),
1066 };
1067 pub const pwr5x: CpuModel = .{
1068 .name = "pwr5x",
1069 .llvm_name = "pwr5x",
1070 .features = featureSet(&[_]Feature{
1071 .@"64bit_support",
1072 .altivec,
1073 .fprnd,
1074 .fre,
1075 .fres,
1076 .frsqrte,
1077 .frsqrtes,
1078 .fsqrt,
1079 .mfocrf,
1080 .stfiwx,
1081 }),
1082 };
1083 pub const pwr6: CpuModel = .{
1084 .name = "pwr6",
1085 .llvm_name = "pwr6",
1086 .features = featureSet(&[_]Feature{
1087 .@"64bit_support",
1088 .altivec,
1089 .cmpb,
1090 .fcpsgn,
1091 .fprnd,
1092 .fre,
1093 .fres,
1094 .frsqrte,
1095 .frsqrtes,
1096 .fsqrt,
1097 .lfiwax,
1098 .mfocrf,
1099 .recipprec,
1100 .stfiwx,
1101 }),
1102 };
1103 pub const pwr6x: CpuModel = .{
1104 .name = "pwr6x",
1105 .llvm_name = "pwr6x",
1106 .features = featureSet(&[_]Feature{
1107 .@"64bit_support",
1108 .altivec,
1109 .cmpb,
1110 .fcpsgn,
1111 .fprnd,
1112 .fre,
1113 .fres,
1114 .frsqrte,
1115 .frsqrtes,
1116 .fsqrt,
1117 .lfiwax,
1118 .mfocrf,
1119 .recipprec,
1120 .stfiwx,
1121 }),
1122 };
1123 pub const pwr7: CpuModel = .{
1124 .name = "pwr7",
1125 .llvm_name = "pwr7",
1126 .features = featureSet(&[_]Feature{
1127 .@"64bit_support",
1128 .allow_unaligned_fp_access,
1129 .bpermd,
1130 .cmpb,
1131 .extdiv,
1132 .fcpsgn,
1133 .fpcvt,
1134 .fprnd,
1135 .fre,
1136 .fres,
1137 .frsqrte,
1138 .frsqrtes,
1139 .fsqrt,
1140 .isa_v206_instructions,
1141 .isel,
1142 .ldbrx,
1143 .lfiwax,
1144 .mfocrf,
1145 .popcntd,
1146 .recipprec,
1147 .stfiwx,
1148 .two_const_nr,
1149 .vsx,
1150 }),
1151 };
1152 pub const pwr8: CpuModel = .{
1153 .name = "pwr8",
1154 .llvm_name = "pwr8",
1155 .features = featureSet(&[_]Feature{
1156 .@"64bit_support",
1157 .allow_unaligned_fp_access,
1158 .bpermd,
1159 .cmpb,
1160 .crbits,
1161 .crypto,
1162 .direct_move,
1163 .extdiv,
1164 .fcpsgn,
1165 .fpcvt,
1166 .fprnd,
1167 .fre,
1168 .fres,
1169 .frsqrte,
1170 .frsqrtes,
1171 .fsqrt,
1172 .fuse_addi_load,
1173 .fuse_addis_load,
1174 .htm,
1175 .icbt,
1176 .isa_v206_instructions,
1177 .isa_v207_instructions,
1178 .isel,
1179 .ldbrx,
1180 .lfiwax,
1181 .mfocrf,
1182 .partword_atomics,
1183 .popcntd,
1184 .power8_vector,
1185 .predictable_select_expensive,
1186 .quadword_atomics,
1187 .recipprec,
1188 .stfiwx,
1189 .two_const_nr,
1190 }),
1191 };
1192 pub const pwr9: CpuModel = .{
1193 .name = "pwr9",
1194 .llvm_name = "pwr9",
1195 .features = featureSet(&[_]Feature{
1196 .@"64bit_support",
1197 .allow_unaligned_fp_access,
1198 .bpermd,
1199 .cmpb,
1200 .crbits,
1201 .crypto,
1202 .direct_move,
1203 .extdiv,
1204 .fcpsgn,
1205 .fpcvt,
1206 .fprnd,
1207 .fre,
1208 .fres,
1209 .frsqrte,
1210 .frsqrtes,
1211 .fsqrt,
1212 .htm,
1213 .icbt,
1214 .isa_v206_instructions,
1215 .isel,
1216 .ldbrx,
1217 .lfiwax,
1218 .mfocrf,
1219 .partword_atomics,
1220 .popcntd,
1221 .power9_vector,
1222 .ppc_postra_sched,
1223 .ppc_prera_sched,
1224 .predictable_select_expensive,
1225 .quadword_atomics,
1226 .recipprec,
1227 .stfiwx,
1228 .two_const_nr,
1229 .vectors_use_two_units,
1230 }),
1231 };
1232};