1pub fn addCases(cases: *tests.LlvmIrContext) void {
2 cases.addMatches("nonnull ptr load",
3 \\export fn entry(ptr: *i16) i16 {
4 \\ return ptr.*;
5 \\}
6 , &.{
7 "ptr nonnull",
8 "load i16, ptr %0",
9 }, .{});
10
11 cases.addMatches("nonnull ptr store",
12 \\export fn entry(ptr: *i16) void {
13 \\ ptr.* = 42;
14 \\}
15 , &.{
16 "ptr nonnull",
17 "store i16 42, ptr %0",
18 }, .{});
19
20 cases.addMatches("unused acquire atomic ptr load",
21 \\export fn entry(ptr: *i16) void {
22 \\ _ = @atomicLoad(i16, ptr, .acquire);
23 \\}
24 , &.{
25 "load atomic i16, ptr %0 acquire",
26 }, .{});
27
28 cases.addMatches("unused unordered atomic volatile ptr load",
29 \\export fn entry(ptr: *volatile i16) void {
30 \\ _ = @atomicLoad(i16, ptr, .unordered);
31 \\}
32 , &.{
33 "load atomic volatile i16, ptr %0 unordered",
34 }, .{});
35
36 cases.addMatches("unused volatile ptr load",
37 \\export fn entry(ptr: *volatile i16) void {
38 \\ _ = ptr.*;
39 \\}
40 , &.{
41 "load volatile i16, ptr %0",
42 }, .{});
43
44 cases.addMatches("dead volatile ptr store",
45 \\export fn entry(ptr: *volatile i16) void {
46 \\ ptr.* = 123;
47 \\ ptr.* = 321;
48 \\}
49 , &.{
50 "store volatile i16 123, ptr %0",
51 "store volatile i16 321, ptr %0",
52 }, .{});
53
54 cases.addMatches("unused volatile slice load",
55 \\export fn entry(ptr: *volatile i16) void {
56 \\ entry2(ptr[0..1]);
57 \\}
58 \\fn entry2(ptr: []volatile i16) void {
59 \\ _ = ptr[0];
60 \\}
61 , &.{
62 "load volatile i16, ptr",
63 }, .{});
64
65 cases.addMatches("dead volatile slice store",
66 \\export fn entry(ptr: *volatile i16) void {
67 \\ entry2(ptr[0..1]);
68 \\}
69 \\fn entry2(ptr: []volatile i16) void {
70 \\ ptr[0] = 123;
71 \\ ptr[0] = 321;
72 \\}
73 , &.{
74 "store volatile i16 123, ptr",
75 "store volatile i16 321, ptr",
76 }, .{});
77
78 cases.addMatches("allowzero ptr load",
79 \\export fn entry(ptr: *allowzero i16) i16 {
80 \\ return ptr.*;
81 \\}
82 , &.{
83 "null_pointer_is_valid",
84 "load i16, ptr %0",
85 }, .{});
86
87 cases.addMatches("allowzero ptr store",
88 \\export fn entry(ptr: *allowzero i16) void {
89 \\ ptr.* = 42;
90 \\}
91 , &.{
92 "null_pointer_is_valid",
93 "store i16 42, ptr %0",
94 }, .{});
95
96 cases.addMatches("allowzero slice load",
97 \\export fn entry(ptr: *allowzero i16) i16 {
98 \\ return entry2(ptr[0..1]);
99 \\}
100 \\fn entry2(ptr: []allowzero i16) i16 {
101 \\ return ptr[0];
102 \\}
103 , &.{
104 "null_pointer_is_valid",
105 "load i16, ptr",
106 }, .{});
107
108 cases.addMatches("allowzero slice store",
109 \\export fn entry(ptr: *allowzero i16) void {
110 \\ entry2(ptr[0..1]);
111 \\}
112 \\fn entry2(ptr: []allowzero i16) void {
113 \\ ptr[0] = 42;
114 \\}
115 , &.{
116 "null_pointer_is_valid",
117 "store i16 42, ptr",
118 }, .{});
119
120 cases.addMatches("load and store bool",
121 \\export fn foo(a: *bool, b: *align(2) bool) void {
122 \\ const tmp = a.*;
123 \\ a.* = b.*;
124 \\ b.* = tmp;
125 \\}
126 , &.{
127 // TODO: this should all be one multiline string literal, but `-femit-llvm-ir` is currently
128 // emitting CRLF on Windows, which is a pain to handle here. In future that option will emit
129 // unoptimized LLVM IR emitted directly from Zig, so that bug will go away.
130 " %3 = load i8, ptr %0, align 1",
131 " %4 = trunc nuw i8 %3 to i1",
132 " %5 = load i8, ptr %1, align 2",
133 " %6 = trunc nuw i8 %5 to i1",
134 " %7 = zext i1 %6 to i8",
135 " store i8 %7, ptr %0, align 1",
136 " %8 = zext i1 %4 to i8",
137 " store i8 %8, ptr %1, align 2",
138 }, .{ .strip = true });
139
140 cases.addMatches("array to vector coercion is one vector load",
141 \\export fn entry(arr: *const [16]u8) @Vector(16, u8) {
142 \\ return arr.*;
143 \\}
144 , &.{
145 "load <16 x i8>, ptr",
146 }, .{});
147
148 cases.addMatches("array to vector coercion feeding overlapping shuffles",
149 \\export fn entry(a: *@Vector(8, u8), b: *@Vector(8, u8), src: [*]const u8) void {
150 \\ const q: @Vector(16, u8) = src[0..16].*;
151 \\ a.* = @shuffle(u8, q, undefined, @Vector(8, i32){ 0, 1, 2, 3, 4, 5, 6, 7 });
152 \\ b.* = @shuffle(u8, q, undefined, @Vector(8, i32){ 7, 8, 9, 10, 11, 12, 13, 14 });
153 \\}
154 , &.{
155 "load <16 x i8>, ptr",
156 "shufflevector <16 x i8>",
157 }, .{});
158}
159
160const std = @import("std");
161const tests = @import("tests.zig");