authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-10-19 23:32:47+02:00
committergravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2025-10-23 09:27:17+02:00
log3e2daa509a897a4e10d5e6f28731b33ac2cc3dc2
tree6475c28a83f4b9495a4554a9bf9b06c8410dbc2f
parentdda05b29c06731895970e75c7444f0d30c7d334f
signaturebadge-check Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM

std.Target: add arceb and xtensaeb Cpu.Arch tags

16 files changed, 173 insertions(+), 115 deletions(-)

lib/std/Target.zig+126-89
......@@ -860,12 +860,14 @@ pub const Abi = enum {
860860
861861 // No musl support.
862862 .arc,
863 .arceb,
863864 => .gnu,
864865 .csky,
865866 => .gnueabi,
866867
867868 // No glibc or musl support.
868869 .xtensa,
870 .xtensaeb,
869871 => .none,
870872
871873 else => .musl,
......@@ -1061,12 +1063,12 @@ pub const ObjectFormat = enum {
10611063
10621064pub fn toElfMachine(target: *const Target) std.elf.EM {
10631065 return switch (target.cpu.arch) {
1066 .aarch64, .aarch64_be => .AARCH64,
10641067 .amdgcn => .AMDGPU,
1065 .arc => .ARC_COMPACT,
1068 .arc, .arceb => .ARC_COMPACT,
10661069 .arm, .armeb, .thumb, .thumbeb => .ARM,
1067 .aarch64, .aarch64_be => .AARCH64,
10681070 .avr => .AVR,
1069 .bpfel, .bpfeb => .BPF,
1071 .bpfeb, .bpfel => .BPF,
10701072 .csky => .CSKY,
10711073 .hexagon => .QDSP6,
10721074 .kalimba => .CSR_KALIMBA,
......@@ -1087,7 +1089,7 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
10871089 .x86 => .@"386",
10881090 .x86_64 => .X86_64,
10891091 .xcore => .XCORE,
1090 .xtensa => .XTENSA,
1092 .xtensa, .xtensaeb => .XTENSA,
10911093
10921094 .nvptx,
10931095 .nvptx64,
......@@ -1118,6 +1120,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
11181120 .aarch64_be,
11191121 .amdgcn,
11201122 .arc,
1123 .arceb,
11211124 .armeb,
11221125 .avr,
11231126 .bpfeb,
......@@ -1149,6 +1152,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
11491152 .wasm64,
11501153 .xcore,
11511154 .xtensa,
1155 .xtensaeb,
11521156 => .UNKNOWN,
11531157 };
11541158}
......@@ -1317,17 +1321,16 @@ pub const Cpu = struct {
13171321 };
13181322
13191323 pub const Arch = enum {
1324 aarch64,
1325 aarch64_be,
13201326 amdgcn,
13211327 arc,
1328 arceb,
13221329 arm,
13231330 armeb,
1324 thumb,
1325 thumbeb,
1326 aarch64,
1327 aarch64_be,
13281331 avr,
1329 bpfel,
13301332 bpfeb,
1333 bpfel,
13311334 csky,
13321335 hexagon,
13331336 kalimba,
......@@ -1340,9 +1343,9 @@ pub const Cpu = struct {
13401343 mips64,
13411344 mips64el,
13421345 msp430,
1343 or1k,
13441346 nvptx,
13451347 nvptx64,
1348 or1k,
13461349 powerpc,
13471350 powerpcle,
13481351 powerpc64,
......@@ -1357,6 +1360,8 @@ pub const Cpu = struct {
13571360 sparc64,
13581361 spirv32,
13591362 spirv64,
1363 thumb,
1364 thumbeb,
13601365 ve,
13611366 wasm32,
13621367 wasm64,
......@@ -1364,6 +1369,7 @@ pub const Cpu = struct {
13641369 x86_64,
13651370 xcore,
13661371 xtensa,
1372 xtensaeb,
13671373
13681374 // LLVM tags deliberately omitted:
13691375 // - aarch64_32
......@@ -1418,12 +1424,12 @@ pub const Cpu = struct {
14181424
14191425 pub inline fn family(arch: Arch) Family {
14201426 return switch (arch) {
1427 .aarch64, .aarch64_be => .aarch64,
14211428 .amdgcn => .amdgcn,
1422 .arc => .arc,
1429 .arc, .arceb => .arc,
14231430 .arm, .armeb, .thumb, .thumbeb => .arm,
1424 .aarch64, .aarch64_be => .aarch64,
14251431 .avr => .avr,
1426 .bpfel, .bpfeb => .bpf,
1432 .bpfeb, .bpfel => .bpf,
14271433 .csky => .csky,
14281434 .hexagon => .hexagon,
14291435 .kalimba => .kalimba,
......@@ -1444,7 +1450,7 @@ pub const Cpu = struct {
14441450 .wasm32, .wasm64 => .wasm,
14451451 .x86, .x86_64 => .x86,
14461452 .xcore => .xcore,
1447 .xtensa => .xtensa,
1453 .xtensa, .xtensaeb => .xtensa,
14481454 };
14491455 }
14501456
......@@ -1477,6 +1483,13 @@ pub const Cpu = struct {
14771483 };
14781484 }
14791485
1486 pub inline fn isArc(arch: Arch) bool {
1487 return switch (arch) {
1488 .arc, .arceb => true,
1489 else => false,
1490 };
1491 }
1492
14801493 pub inline fn isWasm(arch: Arch) bool {
14811494 return switch (arch) {
14821495 .wasm32, .wasm64 => true,
......@@ -1573,6 +1586,13 @@ pub const Cpu = struct {
15731586 };
15741587 }
15751588
1589 pub inline fn isXtensa(arch: Arch) bool {
1590 return switch (arch) {
1591 .xtensa, .xtensaeb => true,
1592 else => false,
1593 };
1594 }
1595
15761596 pub fn parseCpuModel(arch: Arch, cpu_name: []const u8) !*const Cpu.Model {
15771597 for (arch.allCpuModels()) |cpu| {
15781598 if (std.mem.eql(u8, cpu_name, cpu.name)) {
......@@ -1584,43 +1604,39 @@ pub const Cpu = struct {
15841604
15851605 pub fn endian(arch: Arch) std.builtin.Endian {
15861606 return switch (arch) {
1587 .avr,
1588 .arm,
15891607 .aarch64,
1590 .amdgcn,
1608 .arm,
1609 .arc,
1610 .avr,
15911611 .bpfel,
15921612 .csky,
1593 .xtensa,
15941613 .hexagon,
15951614 .kalimba,
1615 .loongarch32,
1616 .loongarch64,
15961617 .mipsel,
15971618 .mips64el,
15981619 .msp430,
1599 .nvptx,
1600 .nvptx64,
16011620 .powerpcle,
16021621 .powerpc64le,
1622 .propeller,
16031623 .riscv32,
16041624 .riscv64,
1605 .x86,
1606 .x86_64,
1625 .thumb,
1626 .ve,
16071627 .wasm32,
16081628 .wasm64,
1629 .x86,
1630 .x86_64,
16091631 .xcore,
1610 .thumb,
1611 .ve,
1612 // GPU bitness is opaque. For now, assume little endian.
1613 .spirv32,
1614 .spirv64,
1615 .loongarch32,
1616 .loongarch64,
1617 .arc,
1618 .propeller,
1632 .xtensa,
16191633 => .little,
16201634
1621 .armeb,
16221635 .aarch64_be,
1636 .arceb,
1637 .armeb,
16231638 .bpfeb,
1639 .lanai,
16241640 .m68k,
16251641 .mips,
16261642 .mips64,
......@@ -1629,12 +1645,20 @@ pub const Cpu = struct {
16291645 .powerpc64,
16301646 .riscv32be,
16311647 .riscv64be,
1648 .s390x,
16321649 .thumbeb,
16331650 .sparc,
16341651 .sparc64,
1635 .lanai,
1636 .s390x,
1652 .xtensaeb,
16371653 => .big,
1654
1655 // GPU endianness is opaque. For now, assume little endian.
1656 .amdgcn,
1657 .nvptx,
1658 .nvptx64,
1659 .spirv32,
1660 .spirv64,
1661 => .little,
16381662 };
16391663 }
16401664
......@@ -1770,7 +1794,7 @@ pub const Cpu = struct {
17701794
17711795 .arc_sysv,
17721796 .arc_interrupt,
1773 => &.{.arc},
1797 => &.{ .arc, .arceb },
17741798
17751799 .avr_gnu,
17761800 .avr_builtin,
......@@ -1826,7 +1850,7 @@ pub const Cpu = struct {
18261850
18271851 .xtensa_call0,
18281852 .xtensa_windowed,
1829 => &.{.xtensa},
1853 => &.{ .xtensa, .xtensaeb },
18301854
18311855 .amdgcn_device,
18321856 .amdgcn_kernel,
......@@ -2418,9 +2442,10 @@ pub const DynamicLinker = struct {
24182442 }
24192443 else if (abi.isGnu())
24202444 switch (cpu.arch) {
2421 // TODO: `eb` architecture support.
24222445 // TODO: `700` ABI support.
2423 .arc => if (abi == .gnu) init("/lib/ld-linux-arc.so.2") else none,
2446 .arc,
2447 .arceb,
2448 => |arch| if (abi == .gnu) initFmt("/lib/ld-linux-{t}.so.2", .{arch}) else none,
24242449
24252450 .arm,
24262451 .armeb,
......@@ -2450,7 +2475,10 @@ pub const DynamicLinker = struct {
24502475 else => return none,
24512476 }}),
24522477
2453 .m68k => if (abi == .gnu) init("/lib/ld.so.1") else none,
2478 .m68k,
2479 .xtensa,
2480 .xtensaeb,
2481 => if (abi == .gnu) init("/lib/ld.so.1") else none,
24542482
24552483 .mips,
24562484 .mipsel,
......@@ -2480,6 +2508,7 @@ pub const DynamicLinker = struct {
24802508 => init("/lib/ld.so.1"),
24812509 else => none,
24822510 },
2511
24832512 .powerpc64,
24842513 .powerpc64le,
24852514 => if (abi == .gnu) init("/lib64/ld64.so.2") else none,
......@@ -2512,8 +2541,6 @@ pub const DynamicLinker = struct {
25122541 else => none,
25132542 },
25142543
2515 .xtensa => if (abi == .gnu) init("/lib/ld.so.1") else none,
2516
25172544 else => none,
25182545 }
25192546 else
......@@ -2680,52 +2707,54 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
26802707 => 16,
26812708
26822709 .arc,
2710 .arceb,
26832711 .arm,
26842712 .armeb,
26852713 .csky,
26862714 .hexagon,
2715 .kalimba,
2716 .lanai,
2717 .loongarch32,
26872718 .m68k,
26882719 .mips,
26892720 .mipsel,
2721 .nvptx,
26902722 .or1k,
26912723 .powerpc,
26922724 .powerpcle,
2725 .propeller,
26932726 .riscv32,
26942727 .riscv32be,
2728 .sparc,
2729 .spirv32,
26952730 .thumb,
26962731 .thumbeb,
2732 .wasm32,
26972733 .x86,
26982734 .xcore,
2699 .nvptx,
2700 .kalimba,
2701 .lanai,
2702 .wasm32,
2703 .sparc,
2704 .spirv32,
2705 .loongarch32,
27062735 .xtensa,
2707 .propeller,
2736 .xtensaeb,
27082737 => 32,
27092738
27102739 .aarch64,
27112740 .aarch64_be,
2741 .amdgcn,
2742 .bpfeb,
2743 .bpfel,
2744 .loongarch64,
27122745 .mips64,
27132746 .mips64el,
2747 .nvptx64,
27142748 .powerpc64,
27152749 .powerpc64le,
27162750 .riscv64,
27172751 .riscv64be,
2718 .x86_64,
2719 .nvptx64,
2720 .wasm64,
2721 .amdgcn,
2722 .bpfel,
2723 .bpfeb,
2724 .sparc64,
27252752 .s390x,
2726 .ve,
2753 .sparc64,
27272754 .spirv64,
2728 .loongarch64,
2755 .ve,
2756 .wasm64,
2757 .x86_64,
27292758 => 64,
27302759 };
27312760}
......@@ -2788,13 +2817,12 @@ pub fn cCharSignedness(target: *const Target) std.builtin.Signedness {
27882817 if (target.os.tag.isDarwin() or target.os.tag == .windows or target.os.tag == .uefi) return .signed;
27892818
27902819 return switch (target.cpu.arch) {
2791 .arm,
2792 .armeb,
2793 .thumb,
2794 .thumbeb,
27952820 .aarch64,
27962821 .aarch64_be,
2822 .arm,
2823 .armeb,
27972824 .arc,
2825 .arceb,
27982826 .csky,
27992827 .hexagon,
28002828 .msp430,
......@@ -2807,8 +2835,11 @@ pub fn cCharSignedness(target: *const Target) std.builtin.Signedness {
28072835 .riscv32be,
28082836 .riscv64,
28092837 .riscv64be,
2838 .thumb,
2839 .thumbeb,
28102840 .xcore,
28112841 .xtensa,
2842 .xtensaeb,
28122843 => .unsigned,
28132844 else => .signed,
28142845 };
......@@ -3217,31 +3248,33 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
32173248 => 2,
32183249
32193250 .arc,
3251 .arceb,
32203252 .csky,
3253 .kalimba,
3254 .or1k,
3255 .propeller,
32213256 .x86,
32223257 .xcore,
3223 .or1k,
3224 .kalimba,
32253258 .xtensa,
3226 .propeller,
3259 .xtensaeb,
32273260 => 4,
32283261
3262 .amdgcn,
32293263 .arm,
32303264 .armeb,
3231 .thumb,
3232 .thumbeb,
3233 .amdgcn,
3234 .bpfel,
32353265 .bpfeb,
3266 .bpfel,
32363267 .hexagon,
3268 .lanai,
32373269 .m68k,
32383270 .mips,
32393271 .mipsel,
3240 .sparc,
3241 .lanai,
32423272 .nvptx,
32433273 .nvptx64,
32443274 .s390x,
3275 .sparc,
3276 .thumb,
3277 .thumbeb,
32453278 => 8,
32463279
32473280 .aarch64,
......@@ -3261,10 +3294,10 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
32613294 .sparc64,
32623295 .spirv32,
32633296 .spirv64,
3264 .x86_64,
32653297 .ve,
32663298 .wasm32,
32673299 .wasm64,
3300 .x86_64,
32683301 => 16,
32693302
32703303 .avr,
......@@ -3276,7 +3309,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) u16 {
32763309pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
32773310 // Overrides for unusual alignments
32783311 switch (target.cpu.arch) {
3279 .arc => switch (c_type) {
3312 .arc, .arceb => switch (c_type) {
32803313 .longdouble => return 4,
32813314 else => {},
32823315 },
......@@ -3315,31 +3348,33 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
33153348 .msp430 => 2,
33163349
33173350 .arc,
3351 .arceb,
33183352 .csky,
3319 .xcore,
3320 .or1k,
33213353 .kalimba,
3322 .xtensa,
3354 .or1k,
33233355 .propeller,
3356 .xcore,
3357 .xtensa,
3358 .xtensaeb,
33243359 => 4,
33253360
3361 .amdgcn,
33263362 .arm,
33273363 .armeb,
3328 .thumb,
3329 .thumbeb,
3330 .amdgcn,
3331 .bpfel,
33323364 .bpfeb,
3365 .bpfel,
33333366 .hexagon,
3334 .x86,
3367 .lanai,
33353368 .m68k,
33363369 .mips,
33373370 .mipsel,
3338 .sparc,
3339 .lanai,
33403371 .nvptx,
33413372 .nvptx64,
33423373 .s390x,
3374 .sparc,
3375 .thumb,
3376 .thumbeb,
3377 .x86,
33433378 => 8,
33443379
33453380 .aarch64,
......@@ -3359,10 +3394,10 @@ pub fn cTypePreferredAlignment(target: *const Target, c_type: CType) u16 {
33593394 .sparc64,
33603395 .spirv32,
33613396 .spirv64,
3362 .x86_64,
33633397 .ve,
33643398 .wasm32,
33653399 .wasm64,
3400 .x86_64,
33663401 => 16,
33673402
33683403 .avr,
......@@ -3378,6 +3413,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
33783413 .msp430 => 2,
33793414
33803415 .arc,
3416 .arceb,
33813417 .csky,
33823418 .kalimba,
33833419 .or1k,
......@@ -3403,6 +3439,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
34033439 .thumbeb,
34043440 .x86,
34053441 .xtensa,
3442 .xtensaeb,
34063443 => 8,
34073444
34083445 .aarch64,
......@@ -3440,9 +3477,9 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
34403477 .windows, .uefi => .{ .x86_win = .{} },
34413478 else => .{ .x86_sysv = .{} },
34423479 },
3443 .aarch64, .aarch64_be => if (target.os.tag.isDarwin()) cc: {
3444 break :cc .{ .aarch64_aapcs_darwin = .{} };
3445 } else switch (target.os.tag) {
3480 .aarch64, .aarch64_be => if (target.os.tag.isDarwin())
3481 .{ .aarch64_aapcs_darwin = .{} }
3482 else switch (target.os.tag) {
34463483 .windows => .{ .aarch64_aapcs_win = .{} },
34473484 else => .{ .aarch64_aapcs = .{} },
34483485 },
......@@ -3469,7 +3506,7 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
34693506 else => .{ .powerpc_sysv = .{} },
34703507 },
34713508 .wasm32, .wasm64 => .{ .wasm_mvp = .{} },
3472 .arc => .{ .arc_sysv = .{} },
3509 .arc, .arceb => .{ .arc_sysv = .{} },
34733510 .avr => .avr_gnu,
34743511 .bpfel, .bpfeb => .{ .bpf_std = .{} },
34753512 .csky => .{ .csky_sysv = .{} },
......@@ -3488,7 +3525,7 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
34883525 .s390x => .{ .s390x_sysv = .{} },
34893526 .ve => .{ .ve_sysv = .{} },
34903527 .xcore => .{ .xcore_xs1 = .{} },
3491 .xtensa => .{ .xtensa_call0 = .{} },
3528 .xtensa, .xtensaeb => .{ .xtensa_call0 = .{} },
34923529 .amdgcn => .{ .amdgcn_device = .{} },
34933530 .nvptx, .nvptx64 => .nvptx_device,
34943531 .spirv32, .spirv64 => .spirv_device,
lib/std/atomic.zig+1
......@@ -419,6 +419,7 @@ pub fn cacheLineForCpu(cpu: std.Target.Cpu) u16 {
419419 .aarch64,
420420 .aarch64_be,
421421 .arc,
422 .arceb,
422423 .powerpc64,
423424 .powerpc64le,
424425 => 128,
lib/std/builtin.zig+4-3
......@@ -275,7 +275,7 @@ pub const CallingConvention = union(enum(u8)) {
275275 /// The standard `wasm32` and `wasm64` calling convention, as specified in the WebAssembly Tool Conventions.
276276 wasm_mvp: CommonOptions,
277277
278 /// The standard `arc` calling convention.
278 /// The standard `arc`/`arceb` calling convention.
279279 arc_sysv: CommonOptions,
280280 arc_interrupt: ArcInterruptOptions,
281281
......@@ -331,7 +331,7 @@ pub const CallingConvention = union(enum(u8)) {
331331 xcore_xs1: CommonOptions,
332332 xcore_xs2: CommonOptions,
333333
334 // Calling conventions for the `xtensa` architecture.
334 // Calling conventions for the `xtensa`/`xtensaeb` architecture.
335335 xtensa_call0: CommonOptions,
336336 xtensa_windowed: CommonOptions,
337337
......@@ -920,6 +920,7 @@ pub const VaList = switch (builtin.cpu.arch) {
920920 .x86,
921921 => *u8,
922922 .arc,
923 .arceb,
923924 .avr,
924925 .bpfel,
925926 .bpfeb,
......@@ -966,7 +967,7 @@ pub const VaList = switch (builtin.cpu.arch) {
966967 },
967968 else => VaListX86_64,
968969 },
969 .xtensa => VaListXtensa,
970 .xtensa, .xtensaeb => VaListXtensa,
970971 else => @compileError("VaList not supported for this target yet"),
971972};
972973
lib/std/builtin/assembly.zig+2-2
......@@ -779,7 +779,7 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {
779779 lr: bool = false,
780780 sr: bool = false,
781781 },
782 .xtensa => packed struct {
782 .xtensa, .xtensaeb => packed struct {
783783 /// Whether the inline assembly code may perform stores to memory
784784 /// addresses other than those derived from input pointer provenance.
785785 memory: bool = false,
......@@ -1591,7 +1591,7 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {
15911591 vr30: bool = false,
15921592 vr31: bool = false,
15931593 },
1594 .arc => packed struct {
1594 .arc, .arceb => packed struct {
15951595 /// Whether the inline assembly code may perform stores to memory
15961596 /// addresses other than those derived from input pointer provenance.
15971597 memory: bool = false,
lib/std/debug/Dwarf.zig+3-3
......@@ -1430,7 +1430,7 @@ pub fn compactUnwindToDwarfRegNumber(unwind_reg_number: u3) !u16 {
14301430pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
14311431 return switch (arch) {
14321432 .aarch64, .aarch64_be => 32,
1433 .arc => 160,
1433 .arc, .arceb => 160,
14341434 .arm, .armeb, .thumb, .thumbeb => 15,
14351435 .csky => 64,
14361436 .hexagon => 76,
......@@ -1453,7 +1453,7 @@ pub fn ipRegNum(arch: std.Target.Cpu.Arch) ?u16 {
14531453pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
14541454 return switch (arch) {
14551455 .aarch64, .aarch64_be => 29,
1456 .arc => 27,
1456 .arc, .arceb => 27,
14571457 .arm, .armeb, .thumb, .thumbeb => 11,
14581458 .csky => 14,
14591459 .hexagon => 30,
......@@ -1476,7 +1476,7 @@ pub fn fpRegNum(arch: std.Target.Cpu.Arch) u16 {
14761476pub fn spRegNum(arch: std.Target.Cpu.Arch) u16 {
14771477 return switch (arch) {
14781478 .aarch64, .aarch64_be => 31,
1479 .arc => 28,
1479 .arc, .arceb => 28,
14801480 .arm, .armeb, .thumb, .thumbeb => 13,
14811481 .csky => 14,
14821482 .hexagon => 29,
lib/std/debug/SelfInfo/Elf.zig+1-1
......@@ -102,7 +102,7 @@ pub const can_unwind: bool = s: {
102102 .x86,
103103 .x86_64,
104104 },
105 // Not supported yet: arm/armeb/thumb/thumbeb, xtensa
105 // Not supported yet: arm/armeb/thumb/thumbeb, xtensa/xtensaeb
106106 .linux => &.{
107107 .aarch64,
108108 .aarch64_be,
lib/std/debug/cpu_context.zig+6-4
......@@ -5,7 +5,7 @@ pub const Native = if (@hasDecl(root, "debug") and @hasDecl(root.debug, "CpuCont
55 root.debug.CpuContext
66else switch (native_arch) {
77 .aarch64, .aarch64_be => Aarch64,
8 .arc => Arc,
8 .arc, .arceb => Arc,
99 .arm, .armeb, .thumb, .thumbeb => Arm,
1010 .csky => Csky,
1111 .hexagon => Hexagon,
......@@ -36,7 +36,7 @@ pub fn fromPosixSignalContext(ctx_ptr: ?*const anyopaque) ?Native {
3636 const uc: *const signal_ucontext_t = @ptrCast(@alignCast(ctx_ptr));
3737
3838 // Deal with some special cases first.
39 if (native_arch == .arc and native_os == .linux) {
39 if (native_arch.isArc() and native_os == .linux) {
4040 var native: Native = .{
4141 .r = [_]u32{ uc.mcontext.r31, uc.mcontext.r30, 0, uc.mcontext.r28 } ++
4242 uc.mcontext.r27_26 ++
......@@ -1553,6 +1553,7 @@ const signal_ucontext_t = switch (native_os) {
15531553 },
15541554 // https://github.com/torvalds/linux/blob/cd5a0afbdf8033dc83786315d63f8b325bdba2fd/include/uapi/asm-generic/ucontext.h
15551555 .arc,
1556 .arceb,
15561557 .csky,
15571558 .hexagon,
15581559 .m68k,
......@@ -1565,13 +1566,14 @@ const signal_ucontext_t = switch (native_os) {
15651566 .x86,
15661567 .x86_64,
15671568 .xtensa,
1569 .xtensaeb,
15681570 => extern struct {
15691571 _flags: usize,
15701572 _link: ?*signal_ucontext_t,
15711573 _stack: std.os.linux.stack_t,
15721574 mcontext: switch (native_arch) {
15731575 // https://github.com/torvalds/linux/blob/cd5a0afbdf8033dc83786315d63f8b325bdba2fd/arch/arc/include/uapi/asm/sigcontext.h
1574 .arc => extern struct {
1576 .arc, .arceb => extern struct {
15751577 _pad1: u32,
15761578 _bta: u32,
15771579 _lp: extern struct {
......@@ -1691,7 +1693,7 @@ const signal_ucontext_t = switch (native_os) {
16911693 rip: u64,
16921694 },
16931695 // https://github.com/torvalds/linux/blob/cd5a0afbdf8033dc83786315d63f8b325bdba2fd/arch/xtensa/include/uapi/asm/sigcontext.h
1694 .xtensa => extern struct {
1696 .xtensa, .xtensaeb => extern struct {
16951697 pc: u32,
16961698 _ps: u32,
16971699 _l: extern struct {
lib/std/heap.zig+4-4
......@@ -824,7 +824,7 @@ const page_size_min_default: ?usize = switch (builtin.os.tag) {
824824 .emscripten => 64 << 10,
825825 .linux => switch (builtin.cpu.arch) {
826826 // Linux/arch/*/Kconfig
827 .arc => 4 << 10,
827 .arc, .arceb => 4 << 10,
828828 .thumb, .thumbeb, .arm, .armeb => 4 << 10,
829829 .aarch64, .aarch64_be => 4 << 10,
830830 .csky => 4 << 10,
......@@ -839,7 +839,7 @@ const page_size_min_default: ?usize = switch (builtin.os.tag) {
839839 .sparc => 4 << 10,
840840 .sparc64 => 8 << 10,
841841 .x86, .x86_64 => 4 << 10,
842 .xtensa => 4 << 10,
842 .xtensa, .xtensaeb => 4 << 10,
843843 else => null,
844844 },
845845 .freestanding, .other => switch (builtin.cpu.arch) {
......@@ -972,7 +972,7 @@ const page_size_max_default: ?usize = switch (builtin.os.tag) {
972972 .emscripten => 64 << 10,
973973 .linux => switch (builtin.cpu.arch) {
974974 // Linux/arch/*/Kconfig
975 .arc => 16 << 10,
975 .arc, .arceb => 16 << 10,
976976 .thumb, .thumbeb, .arm, .armeb => 4 << 10,
977977 .aarch64, .aarch64_be => 64 << 10,
978978 .csky => 4 << 10,
......@@ -987,7 +987,7 @@ const page_size_max_default: ?usize = switch (builtin.os.tag) {
987987 .sparc => 4 << 10,
988988 .sparc64 => 8 << 10,
989989 .x86, .x86_64 => 4 << 10,
990 .xtensa => 4 << 10,
990 .xtensa, .xtensaeb => 4 << 10,
991991 else => null,
992992 },
993993 .freestanding => switch (builtin.cpu.arch) {
lib/std/os/linux.zig+8-3
......@@ -116,7 +116,7 @@ pub const SECCOMP = @import("linux/seccomp.zig");
116116
117117pub const syscalls = @import("linux/syscalls.zig");
118118pub const SYS = switch (native_arch) {
119 .arc => syscalls.Arc,
119 .arc, .arceb => syscalls.Arc,
120120 .aarch64, .aarch64_be => syscalls.Arm64,
121121 .arm, .armeb, .thumb, .thumbeb => syscalls.Arm,
122122 .csky => syscalls.CSky,
......@@ -141,7 +141,7 @@ pub const SYS = switch (native_arch) {
141141 .gnux32, .muslx32 => syscalls.X32,
142142 else => syscalls.X64,
143143 },
144 .xtensa => syscalls.Xtensa,
144 .xtensa, .xtensaeb => syscalls.Xtensa,
145145 else => @compileError("The Zig Standard Library is missing syscall definitions for the target CPU architecture"),
146146};
147147
......@@ -3686,7 +3686,7 @@ pub const PROT = struct {
36863686 pub const EXEC = 0x4;
36873687 /// page may be used for atomic ops
36883688 pub const SEM = switch (native_arch) {
3689 .mips, .mipsel, .mips64, .mips64el, .xtensa => 0x10,
3689 .mips, .mipsel, .mips64, .mips64el, .xtensa, .xtensaeb => 0x10,
36903690 else => 0x8,
36913691 };
36923692 /// mprotect flag: extend change to start of growsdown vma
......@@ -6161,6 +6161,7 @@ pub fn CPU_COUNT(set: cpu_set_t) cpu_count_t {
61616161
61626162pub const MINSIGSTKSZ = switch (native_arch) {
61636163 .arc,
6164 .arceb,
61646165 .arm,
61656166 .armeb,
61666167 .csky,
......@@ -6181,6 +6182,7 @@ pub const MINSIGSTKSZ = switch (native_arch) {
61816182 .x86,
61826183 .x86_64,
61836184 .xtensa,
6185 .xtensaeb,
61846186 => 2048,
61856187 .loongarch64,
61866188 .sparc,
......@@ -6196,6 +6198,7 @@ pub const MINSIGSTKSZ = switch (native_arch) {
61966198};
61976199pub const SIGSTKSZ = switch (native_arch) {
61986200 .arc,
6201 .arceb,
61996202 .arm,
62006203 .armeb,
62016204 .csky,
......@@ -6216,6 +6219,7 @@ pub const SIGSTKSZ = switch (native_arch) {
62166219 .x86,
62176220 .x86_64,
62186221 .xtensa,
6222 .xtensaeb,
62196223 => 8192,
62206224 .aarch64,
62216225 .aarch64_be,
......@@ -9740,6 +9744,7 @@ pub const AUDIT = struct {
97409744 .armeb, .thumbeb => .ARMEB,
97419745 .aarch64 => .AARCH64,
97429746 .arc => .ARCV2,
9747 .arceb => .ARCV2BE,
97439748 .csky => .CSKY,
97449749 .hexagon => .HEXAGON,
97459750 .loongarch32 => .LOONGARCH32,
lib/std/os/linux/tls.zig+2-1
......@@ -64,6 +64,7 @@ const Variant = enum {
6464
6565const current_variant: Variant = switch (native_arch) {
6666 .arc,
67 .arceb,
6768 .arm,
6869 .armeb,
6970 .aarch64,
......@@ -243,7 +244,7 @@ pub fn setThreadPointer(addr: usize) void {
243244 : [addr] "r" (addr),
244245 );
245246 },
246 .arc => {
247 .arc, .arceb => {
247248 // We apparently need to both set r25 (TP) *and* inform the kernel...
248249 asm volatile (
249250 \\ mov r25, %[addr]
lib/std/pie.zig+2-2
......@@ -22,7 +22,7 @@ const R_SPARC_RELATIVE = 22;
2222const R_RELATIVE = switch (builtin.cpu.arch) {
2323 .x86 => R_386_RELATIVE,
2424 .x86_64 => R_AMD64_RELATIVE,
25 .arc => R_ARC_RELATIVE,
25 .arc, .arceb => R_ARC_RELATIVE,
2626 .arm, .armeb, .thumb, .thumbeb => R_ARM_RELATIVE,
2727 .aarch64, .aarch64_be => R_AARCH64_RELATIVE,
2828 .csky => R_CSKY_RELATIVE,
......@@ -58,7 +58,7 @@ inline fn getDynamicSymbol() [*]const elf.Dyn {
5858 \\ lea _DYNAMIC(%%rip), %[ret]
5959 : [ret] "=r" (-> [*]const elf.Dyn),
6060 ),
61 .arc => asm volatile (
61 .arc, .arceb => asm volatile (
6262 \\ .weak _DYNAMIC
6363 \\ .hidden _DYNAMIC
6464 \\ add %[ret], pcl, _DYNAMIC@pcl
lib/std/start.zig+2-2
......@@ -195,7 +195,7 @@ fn _start() callconv(.naked) noreturn {
195195 // This is the first userspace frame. Prevent DWARF-based unwinders from unwinding further. We
196196 // prevent FP-based unwinders from unwinding further by zeroing the register below.
197197 if (builtin.unwind_tables != .none or !builtin.strip_debug_info) asm volatile (switch (native_arch) {
198 .arc => ".cfi_undefined blink",
198 .arc, .arceb => ".cfi_undefined blink",
199199 .arm, .armeb, .thumb, .thumbeb => "", // https://github.com/llvm/llvm-project/issues/115891
200200 .aarch64, .aarch64_be => ".cfi_undefined lr",
201201 .csky => ".cfi_undefined lr",
......@@ -253,7 +253,7 @@ fn _start() callconv(.naked) noreturn {
253253 \\ and sp, x0, #-16
254254 \\ b %[posixCallMainAndExit]
255255 ,
256 .arc =>
256 .arc, .arceb =>
257257 // ARC v1 and v2 had a very low stack alignment requirement of 4; v3 increased it to 16.
258258 \\ mov fp, 0
259259 \\ mov blink, 0
lib/std/zig/system.zig+1
......@@ -119,6 +119,7 @@ pub fn getExternalExecutor(
119119 .thumb,
120120 .thumbeb,
121121 .xtensa,
122 .xtensaeb,
122123 => |t| switch (candidate.os.tag) {
123124 .linux,
124125 => .{ .qemu = switch (t) {
src/codegen/llvm.zig+6
......@@ -106,9 +106,11 @@ pub fn targetTriple(allocator: Allocator, target: *const std.Target) ![]const u8
106106 .wasm64 => "wasm64",
107107 .ve => "ve",
108108
109 .arceb,
109110 .kalimba,
110111 .or1k,
111112 .propeller,
113 .xtensaeb,
112114 => unreachable, // Gated by hasLlvmSupport().
113115 };
114116
......@@ -473,9 +475,11 @@ pub fn dataLayout(target: *const std.Target) []const u8 {
473475 .loongarch64 => "e-m:e-p:64:64-i64:64-i128:128-n32:64-S128",
474476 .xtensa => "e-m:e-p:32:32-i8:8:32-i16:16:32-i64:64-n32",
475477
478 .arceb,
476479 .kalimba,
477480 .or1k,
478481 .propeller,
482 .xtensaeb,
479483 => unreachable, // Gated by hasLlvmSupport().
480484 };
481485}
......@@ -13107,9 +13111,11 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
1310713111 },
1310813112
1310913113 // LLVM does does not have a backend for these.
13114 .arceb,
1311013115 .kalimba,
1311113116 .or1k,
1311213117 .propeller,
13118 .xtensaeb,
1311313119 => unreachable,
1311413120 }
1311513121}
src/target.zig+4
......@@ -216,9 +216,11 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)
216216 => false,
217217
218218 // No LLVM backend exists.
219 .arceb,
219220 .kalimba,
220221 .or1k,
221222 .propeller,
223 .xtensaeb,
222224 => false,
223225 };
224226}
......@@ -711,6 +713,7 @@ pub fn minFunctionAlignment(target: *const std.Target) Alignment {
711713 .xcore,
712714 => .@"2",
713715 .arc,
716 .arceb,
714717 .arm,
715718 .armeb,
716719 .aarch64,
......@@ -728,6 +731,7 @@ pub fn minFunctionAlignment(target: *const std.Target) Alignment {
728731 .sparc,
729732 .sparc64,
730733 .xtensa,
734 .xtensaeb,
731735 => .@"4",
732736 .bpfel,
733737 .bpfeb,
test/tests.zig+1-1
......@@ -1550,7 +1550,7 @@ const CAbiTarget = struct {
15501550};
15511551
15521552const c_abi_targets = blk: {
1553 @setEvalBranchQuota(20000);
1553 @setEvalBranchQuota(30000);
15541554 break :blk [_]CAbiTarget{
15551555 // Native Targets
15561556