authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-11-04 13:54:56+01:00
committergravatar for noreply@github.comGitHub <noreply@github.com> 2024-11-04 13:54:56+01:00
log4a3611f7d6837da6a27df22e631838fd60819768
tree23889b748d20184dffb31a2f8725adeaa74fbade
parent6b2c8fc6886cdf251146aa3674e87f6ca3111e24
parentaf71694dd946a88bf0db55e4513223e344bfde40
signaturebadge-check Signed by PGP key B5690EEEBB952194

Merge pull request #21894 from alexrp/aarch64-big-endian

Disable some failing tests and add `aarch64_be-linux-(none,gnu,musl)` to CI

10 files changed, 54 insertions(+), 21 deletions(-)

lib/std/debug.zig+4
...@@ -1335,7 +1335,11 @@ fn dumpSegfaultInfoPosix(sig: i32, code: i32, addr: usize, ctx_ptr: ?*anyopaque)...@@ -1335,7 +1335,11 @@ fn dumpSegfaultInfoPosix(sig: i32, code: i32, addr: usize, ctx_ptr: ?*anyopaque)
1335 .x86,1335 .x86,
1336 .x86_64,1336 .x86_64,
1337 .arm,1337 .arm,
1338 .armeb,
1339 .thumb,
1340 .thumbeb,
1338 .aarch64,1341 .aarch64,
1342 .aarch64_be,
1339 => {1343 => {
1340 const ctx: *posix.ucontext_t = @ptrCast(@alignCast(ctx_ptr));1344 const ctx: *posix.ucontext_t = @ptrCast(@alignCast(ctx_ptr));
1341 dumpStackTraceFromBase(ctx);1345 dumpStackTraceFromBase(ctx);
lib/std/debug/Dwarf/abi.zig+9-9
...@@ -35,8 +35,8 @@ pub fn ipRegNum(arch: Arch) ?u8 {...@@ -35,8 +35,8 @@ pub fn ipRegNum(arch: Arch) ?u8 {
35 return switch (arch) {35 return switch (arch) {
36 .x86 => 8,36 .x86 => 8,
37 .x86_64 => 16,37 .x86_64 => 16,
38 .arm => 15,38 .arm, .armeb, .thumb, .thumbeb => 15,
39 .aarch64 => 32,39 .aarch64, .aarch64_be => 32,
40 else => null,40 else => null,
41 };41 };
42}42}
...@@ -47,8 +47,8 @@ pub fn fpRegNum(arch: Arch, reg_context: RegisterContext) u8 {...@@ -47,8 +47,8 @@ pub fn fpRegNum(arch: Arch, reg_context: RegisterContext) u8 {
47 // (only in .eh_frame), and that is now the convention for MachO47 // (only in .eh_frame), and that is now the convention for MachO
48 .x86 => if (reg_context.eh_frame and reg_context.is_macho) 4 else 5,48 .x86 => if (reg_context.eh_frame and reg_context.is_macho) 4 else 5,
49 .x86_64 => 6,49 .x86_64 => 6,
50 .arm => 11,50 .arm, .armeb, .thumb, .thumbeb => 11,
51 .aarch64 => 29,51 .aarch64, .aarch64_be => 29,
52 else => unreachable,52 else => unreachable,
53 };53 };
54}54}
...@@ -57,8 +57,8 @@ pub fn spRegNum(arch: Arch, reg_context: RegisterContext) u8 {...@@ -57,8 +57,8 @@ pub fn spRegNum(arch: Arch, reg_context: RegisterContext) u8 {
57 return switch (arch) {57 return switch (arch) {
58 .x86 => if (reg_context.eh_frame and reg_context.is_macho) 5 else 4,58 .x86 => if (reg_context.eh_frame and reg_context.is_macho) 5 else 4,
59 .x86_64 => 7,59 .x86_64 => 7,
60 .arm => 13,60 .arm, .armeb, .thumb, .thumbeb => 13,
61 .aarch64 => 31,61 .aarch64, .aarch64_be => 31,
62 else => unreachable,62 else => unreachable,
63 };63 };
64}64}
...@@ -131,7 +131,7 @@ pub fn regBytes(...@@ -131,7 +131,7 @@ pub fn regBytes(
131 16 => mem.asBytes(&thread_context_ptr.Rip),131 16 => mem.asBytes(&thread_context_ptr.Rip),
132 else => error.InvalidRegister,132 else => error.InvalidRegister,
133 },133 },
134 .aarch64 => switch (reg_number) {134 .aarch64, .aarch64_be => switch (reg_number) {
135 0...30 => mem.asBytes(&thread_context_ptr.DUMMYUNIONNAME.X[reg_number]),135 0...30 => mem.asBytes(&thread_context_ptr.DUMMYUNIONNAME.X[reg_number]),
136 31 => mem.asBytes(&thread_context_ptr.Sp),136 31 => mem.asBytes(&thread_context_ptr.Sp),
137 32 => mem.asBytes(&thread_context_ptr.Pc),137 32 => mem.asBytes(&thread_context_ptr.Pc),
...@@ -269,7 +269,7 @@ pub fn regBytes(...@@ -269,7 +269,7 @@ pub fn regBytes(
269 },269 },
270 else => error.UnimplementedOs,270 else => error.UnimplementedOs,
271 },271 },
272 .arm => switch (builtin.os.tag) {272 .arm, .armeb, .thumb, .thumbeb => switch (builtin.os.tag) {
273 .linux => switch (reg_number) {273 .linux => switch (reg_number) {
274 0 => mem.asBytes(&ucontext_ptr.mcontext.arm_r0),274 0 => mem.asBytes(&ucontext_ptr.mcontext.arm_r0),
275 1 => mem.asBytes(&ucontext_ptr.mcontext.arm_r1),275 1 => mem.asBytes(&ucontext_ptr.mcontext.arm_r1),
...@@ -292,7 +292,7 @@ pub fn regBytes(...@@ -292,7 +292,7 @@ pub fn regBytes(
292 },292 },
293 else => error.UnimplementedOs,293 else => error.UnimplementedOs,
294 },294 },
295 .aarch64 => switch (builtin.os.tag) {295 .aarch64, .aarch64_be => switch (builtin.os.tag) {
296 .macos, .ios, .watchos => switch (reg_number) {296 .macos, .ios, .watchos => switch (reg_number) {
297 0...28 => mem.asBytes(&ucontext_ptr.mcontext.ss.regs[reg_number]),297 0...28 => mem.asBytes(&ucontext_ptr.mcontext.ss.regs[reg_number]),
298 29 => mem.asBytes(&ucontext_ptr.mcontext.ss.fp),298 29 => mem.asBytes(&ucontext_ptr.mcontext.ss.fp),
lib/std/debug/SelfInfo.zig+5-5
...@@ -1419,7 +1419,7 @@ pub fn unwindFrameMachO(...@@ -1419,7 +1419,7 @@ pub fn unwindFrameMachO(
1419 return unwindFrameMachODwarf(context, ma, eh_frame orelse return error.MissingEhFrame, @intCast(encoding.value.x86_64.dwarf));1419 return unwindFrameMachODwarf(context, ma, eh_frame orelse return error.MissingEhFrame, @intCast(encoding.value.x86_64.dwarf));
1420 },1420 },
1421 },1421 },
1422 .aarch64 => switch (encoding.mode.arm64) {1422 .aarch64, .aarch64_be => switch (encoding.mode.arm64) {
1423 .OLD => return error.UnimplementedUnwindEncoding,1423 .OLD => return error.UnimplementedUnwindEncoding,
1424 .FRAMELESS => blk: {1424 .FRAMELESS => blk: {
1425 const sp = (try regValueNative(context.thread_context, spRegNum(reg_context), reg_context)).*;1425 const sp = (try regValueNative(context.thread_context, spRegNum(reg_context), reg_context)).*;
...@@ -1535,7 +1535,7 @@ pub const UnwindContext = struct {...@@ -1535,7 +1535,7 @@ pub const UnwindContext = struct {
1535/// Some platforms use pointer authentication - the upper bits of instruction pointers contain a signature.1535/// Some platforms use pointer authentication - the upper bits of instruction pointers contain a signature.
1536/// This function clears these signature bits to make the pointer usable.1536/// This function clears these signature bits to make the pointer usable.
1537pub inline fn stripInstructionPtrAuthCode(ptr: usize) usize {1537pub inline fn stripInstructionPtrAuthCode(ptr: usize) usize {
1538 if (native_arch == .aarch64) {1538 if (native_arch.isAARCH64()) {
1539 // `hint 0x07` maps to `xpaclri` (or `nop` if the hardware doesn't support it)1539 // `hint 0x07` maps to `xpaclri` (or `nop` if the hardware doesn't support it)
1540 // The save / restore is because `xpaclri` operates on x30 (LR)1540 // The save / restore is because `xpaclri` operates on x30 (LR)
1541 return asm (1541 return asm (
...@@ -1787,11 +1787,11 @@ pub fn supportsUnwinding(target: std.Target) bool {...@@ -1787,11 +1787,11 @@ pub fn supportsUnwinding(target: std.Target) bool {
1787 .linux, .netbsd, .freebsd, .openbsd, .macos, .ios, .solaris, .illumos => true,1787 .linux, .netbsd, .freebsd, .openbsd, .macos, .ios, .solaris, .illumos => true,
1788 else => false,1788 else => false,
1789 },1789 },
1790 .arm => switch (target.os.tag) {1790 .arm, .armeb, .thumb, .thumbeb => switch (target.os.tag) {
1791 .linux => true,1791 .linux => true,
1792 else => false,1792 else => false,
1793 },1793 },
1794 .aarch64 => switch (target.os.tag) {1794 .aarch64, .aarch64_be => switch (target.os.tag) {
1795 .linux, .netbsd, .freebsd, .macos, .ios => true,1795 .linux, .netbsd, .freebsd, .macos, .ios => true,
1796 else => false,1796 else => false,
1797 },1797 },
...@@ -2194,7 +2194,7 @@ pub const VirtualMachine = struct {...@@ -2194,7 +2194,7 @@ pub const VirtualMachine = struct {
2194/// the .undefined rule by default, but allows ABI authors to override that.2194/// the .undefined rule by default, but allows ABI authors to override that.
2195fn getRegDefaultValue(reg_number: u8, context: *UnwindContext, out: []u8) !void {2195fn getRegDefaultValue(reg_number: u8, context: *UnwindContext, out: []u8) !void {
2196 switch (builtin.cpu.arch) {2196 switch (builtin.cpu.arch) {
2197 .aarch64 => {2197 .aarch64, .aarch64_be => {
2198 // Callee-saved registers are initialized as if they had the .same_value rule2198 // Callee-saved registers are initialized as if they had the .same_value rule
2199 if (reg_number >= 19 and reg_number <= 28) {2199 if (reg_number >= 19 and reg_number <= 28) {
2200 const src = try regBytes(context.thread_context, reg_number, context.reg_context);2200 const src = try regBytes(context.thread_context, reg_number, context.reg_context);
lib/std/simd.zig+1
...@@ -462,6 +462,7 @@ pub fn prefixScan(comptime op: std.builtin.ReduceOp, comptime hop: isize, vec: a...@@ -462,6 +462,7 @@ pub fn prefixScan(comptime op: std.builtin.ReduceOp, comptime hop: isize, vec: a
462462
463test "vector prefix scan" {463test "vector prefix scan" {
464 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;464 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
465 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21893
465466
466 if (comptime builtin.cpu.arch.isMIPS()) {467 if (comptime builtin.cpu.arch.isMIPS()) {
467 return error.SkipZigTest;468 return error.SkipZigTest;
test/behavior/atomics.zig+2-1
...@@ -5,7 +5,8 @@ const expectEqual = std.testing.expectEqual;...@@ -5,7 +5,8 @@ const expectEqual = std.testing.expectEqual;
55
6const supports_128_bit_atomics = switch (builtin.cpu.arch) {6const supports_128_bit_atomics = switch (builtin.cpu.arch) {
7 // TODO: Ideally this could be sync'd with the logic in Sema.7 // TODO: Ideally this could be sync'd with the logic in Sema.
8 .aarch64, .aarch64_be => true,8 .aarch64 => true,
9 .aarch64_be => false, // Fails due to LLVM issues.
9 .x86_64 => std.Target.x86.featureSetHas(builtin.cpu.features, .cx16),10 .x86_64 => std.Target.x86.featureSetHas(builtin.cpu.features, .cx16),
10 else => false,11 else => false,
11};12};
test/behavior/bitcast.zig+1
...@@ -402,6 +402,7 @@ test "bitcast vector to integer and back" {...@@ -402,6 +402,7 @@ test "bitcast vector to integer and back" {
402 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO402 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
403 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;403 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
404 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;404 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
405 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
405406
406 const arr: [16]bool = [_]bool{ true, false } ++ [_]bool{true} ** 14;407 const arr: [16]bool = [_]bool{ true, false } ++ [_]bool{true} ** 14;
407 var x: @Vector(16, bool) = @splat(true);408 var x: @Vector(16, bool) = @splat(true);
test/behavior/union.zig+1-3
...@@ -1820,10 +1820,8 @@ test "reinterpret packed union" {...@@ -1820,10 +1820,8 @@ test "reinterpret packed union" {
1820 try comptime S.doTheTest();1820 try comptime S.doTheTest();
18211821
1822 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO1822 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
1823 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21050
1824 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21050
1825 if (builtin.cpu.arch.isWasm()) return error.SkipZigTest; // TODO1823 if (builtin.cpu.arch.isWasm()) return error.SkipZigTest; // TODO
1826 if (builtin.cpu.arch == .s390x and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // TODO1824 if (builtin.cpu.arch.endian() == .big) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21050
1827 try S.doTheTest();1825 try S.doTheTest();
1828}1826}
18291827
test/behavior/vector.zig+7
...@@ -1060,6 +1060,7 @@ test "@addWithOverflow" {...@@ -1060,6 +1060,7 @@ test "@addWithOverflow" {
1060 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO1060 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1061 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO1061 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
1062 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;1062 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1063 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
10631064
1064 const S = struct {1065 const S = struct {
1065 fn doTheTest() !void {1066 fn doTheTest() !void {
...@@ -1108,6 +1109,7 @@ test "@subWithOverflow" {...@@ -1108,6 +1109,7 @@ test "@subWithOverflow" {
1108 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO1109 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1109 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO1110 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
1110 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;1111 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1112 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
11111113
1112 const S = struct {1114 const S = struct {
1113 fn doTheTest() !void {1115 fn doTheTest() !void {
...@@ -1140,6 +1142,7 @@ test "@mulWithOverflow" {...@@ -1140,6 +1142,7 @@ test "@mulWithOverflow" {
1140 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO1142 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1141 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO1143 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
1142 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;1144 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1145 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
11431146
1144 const S = struct {1147 const S = struct {
1145 fn doTheTest() !void {1148 fn doTheTest() !void {
...@@ -1162,6 +1165,7 @@ test "@shlWithOverflow" {...@@ -1162,6 +1165,7 @@ test "@shlWithOverflow" {
1162 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO1165 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1163 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO1166 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
1164 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;1167 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1168 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
11651169
1166 const S = struct {1170 const S = struct {
1167 fn doTheTest() !void {1171 fn doTheTest() !void {
...@@ -1245,6 +1249,7 @@ test "byte vector initialized in inline function" {...@@ -1245,6 +1249,7 @@ test "byte vector initialized in inline function" {
1245 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO1249 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
1246 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO1250 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
1247 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;1251 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1252 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
12481253
1249 if (comptime builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .x86_64 and1254 if (comptime builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .x86_64 and
1250 builtin.cpu.features.isEnabled(@intFromEnum(std.Target.x86.Feature.avx512f)))1255 builtin.cpu.features.isEnabled(@intFromEnum(std.Target.x86.Feature.avx512f)))
...@@ -1370,6 +1375,7 @@ test "store packed vector element" {...@@ -1370,6 +1375,7 @@ test "store packed vector element" {
1370 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO1375 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
1371 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO1376 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
1372 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;1377 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1378 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
13731379
1374 var v = @Vector(4, u1){ 1, 1, 1, 1 };1380 var v = @Vector(4, u1){ 1, 1, 1, 1 };
1375 try expectEqual(@Vector(4, u1){ 1, 1, 1, 1 }, v);1381 try expectEqual(@Vector(4, u1){ 1, 1, 1, 1 }, v);
...@@ -1406,6 +1412,7 @@ test "store vector with memset" {...@@ -1406,6 +1412,7 @@ test "store vector with memset" {
1406 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO1412 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
1407 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO1413 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
1408 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;1414 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1415 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
14091416
1410 var a: [5]@Vector(2, i1) = undefined;1417 var a: [5]@Vector(2, i1) = undefined;
1411 var b: [5]@Vector(2, u2) = undefined;1418 var b: [5]@Vector(2, u2) = undefined;
test/llvm_targets.zig-3
...@@ -225,7 +225,6 @@ const targets = [_]std.Target.Query{...@@ -225,7 +225,6 @@ const targets = [_]std.Target.Query{
225 .{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .gnu },225 .{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .gnu },
226 .{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .musl },226 .{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .musl },
227 .{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .none },227 .{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .none },
228 .{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .ohos },
229 .{ .cpu_arch = .riscv32, .os_tag = .rtems, .abi = .none },228 .{ .cpu_arch = .riscv32, .os_tag = .rtems, .abi = .none },
230 .{ .cpu_arch = .riscv32, .os_tag = .uefi, .abi = .none },229 .{ .cpu_arch = .riscv32, .os_tag = .uefi, .abi = .none },
231230
...@@ -238,7 +237,6 @@ const targets = [_]std.Target.Query{...@@ -238,7 +237,6 @@ const targets = [_]std.Target.Query{
238 .{ .cpu_arch = .riscv64, .os_tag = .linux, .abi = .gnu },237 .{ .cpu_arch = .riscv64, .os_tag = .linux, .abi = .gnu },
239 .{ .cpu_arch = .riscv64, .os_tag = .linux, .abi = .musl },238 .{ .cpu_arch = .riscv64, .os_tag = .linux, .abi = .musl },
240 .{ .cpu_arch = .riscv64, .os_tag = .linux, .abi = .none },239 .{ .cpu_arch = .riscv64, .os_tag = .linux, .abi = .none },
241 .{ .cpu_arch = .riscv64, .os_tag = .linux, .abi = .ohos },
242 .{ .cpu_arch = .riscv64, .os_tag = .netbsd, .abi = .none },240 .{ .cpu_arch = .riscv64, .os_tag = .netbsd, .abi = .none },
243 .{ .cpu_arch = .riscv64, .os_tag = .openbsd, .abi = .none },241 .{ .cpu_arch = .riscv64, .os_tag = .openbsd, .abi = .none },
244 .{ .cpu_arch = .riscv64, .os_tag = .rtems, .abi = .none },242 .{ .cpu_arch = .riscv64, .os_tag = .rtems, .abi = .none },
...@@ -326,7 +324,6 @@ const targets = [_]std.Target.Query{...@@ -326,7 +324,6 @@ const targets = [_]std.Target.Query{
326 .{ .cpu_arch = .x86, .os_tag = .linux, .abi = .gnu },324 .{ .cpu_arch = .x86, .os_tag = .linux, .abi = .gnu },
327 .{ .cpu_arch = .x86, .os_tag = .linux, .abi = .musl },325 .{ .cpu_arch = .x86, .os_tag = .linux, .abi = .musl },
328 .{ .cpu_arch = .x86, .os_tag = .linux, .abi = .none },326 .{ .cpu_arch = .x86, .os_tag = .linux, .abi = .none },
329 .{ .cpu_arch = .x86, .os_tag = .linux, .abi = .ohos },
330 .{ .cpu_arch = .x86, .os_tag = .netbsd, .abi = .none },327 .{ .cpu_arch = .x86, .os_tag = .netbsd, .abi = .none },
331 .{ .cpu_arch = .x86, .os_tag = .openbsd, .abi = .none },328 .{ .cpu_arch = .x86, .os_tag = .openbsd, .abi = .none },
332 .{ .cpu_arch = .x86, .os_tag = .rtems, .abi = .none },329 .{ .cpu_arch = .x86, .os_tag = .rtems, .abi = .none },
test/tests.zig+24
...@@ -291,6 +291,30 @@ const test_targets = blk: {...@@ -291,6 +291,30 @@ const test_targets = blk: {
291 .link_libc = true,291 .link_libc = true,
292 },292 },
293293
294 .{
295 .target = .{
296 .cpu_arch = .aarch64_be,
297 .os_tag = .linux,
298 .abi = .none,
299 },
300 },
301 .{
302 .target = .{
303 .cpu_arch = .aarch64_be,
304 .os_tag = .linux,
305 .abi = .musl,
306 },
307 .link_libc = true,
308 },
309 .{
310 .target = .{
311 .cpu_arch = .aarch64_be,
312 .os_tag = .linux,
313 .abi = .gnu,
314 },
315 .link_libc = true,
316 },
317
294 .{318 .{
295 .target = .{319 .target = .{
296 .cpu_arch = .arm,320 .cpu_arch = .arm,