authorgravatar for alex@alexrp.comAlex Rønne Petersen <alex@alexrp.com> 2024-11-04 13:54:56+01:00
committergravatar for noreply@github.comGitHub <noreply@github.com> 2024-11-04 13:54:56+01:00
log4a3611f7d6837da6a27df22e631838fd60819768
tree23889b748d20184dffb31a2f8725adeaa74fbade
parent6b2c8fc6886cdf251146aa3674e87f6ca3111e24
parentaf71694dd946a88bf0db55e4513223e344bfde40
signaturebadge-check Signed by PGP key B5690EEEBB952194

Merge pull request #21894 from alexrp/aarch64-big-endian

Disable some failing tests and add `aarch64_be-linux-(none,gnu,musl)` to CI

10 files changed, 54 insertions(+), 21 deletions(-)

lib/std/debug.zig+4
......@@ -1335,7 +1335,11 @@ fn dumpSegfaultInfoPosix(sig: i32, code: i32, addr: usize, ctx_ptr: ?*anyopaque)
13351335 .x86,
13361336 .x86_64,
13371337 .arm,
1338 .armeb,
1339 .thumb,
1340 .thumbeb,
13381341 .aarch64,
1342 .aarch64_be,
13391343 => {
13401344 const ctx: *posix.ucontext_t = @ptrCast(@alignCast(ctx_ptr));
13411345 dumpStackTraceFromBase(ctx);
lib/std/debug/Dwarf/abi.zig+9-9
......@@ -35,8 +35,8 @@ pub fn ipRegNum(arch: Arch) ?u8 {
3535 return switch (arch) {
3636 .x86 => 8,
3737 .x86_64 => 16,
38 .arm => 15,
39 .aarch64 => 32,
38 .arm, .armeb, .thumb, .thumbeb => 15,
39 .aarch64, .aarch64_be => 32,
4040 else => null,
4141 };
4242}
......@@ -47,8 +47,8 @@ pub fn fpRegNum(arch: Arch, reg_context: RegisterContext) u8 {
4747 // (only in .eh_frame), and that is now the convention for MachO
4848 .x86 => if (reg_context.eh_frame and reg_context.is_macho) 4 else 5,
4949 .x86_64 => 6,
50 .arm => 11,
51 .aarch64 => 29,
50 .arm, .armeb, .thumb, .thumbeb => 11,
51 .aarch64, .aarch64_be => 29,
5252 else => unreachable,
5353 };
5454}
......@@ -57,8 +57,8 @@ pub fn spRegNum(arch: Arch, reg_context: RegisterContext) u8 {
5757 return switch (arch) {
5858 .x86 => if (reg_context.eh_frame and reg_context.is_macho) 5 else 4,
5959 .x86_64 => 7,
60 .arm => 13,
61 .aarch64 => 31,
60 .arm, .armeb, .thumb, .thumbeb => 13,
61 .aarch64, .aarch64_be => 31,
6262 else => unreachable,
6363 };
6464}
......@@ -131,7 +131,7 @@ pub fn regBytes(
131131 16 => mem.asBytes(&thread_context_ptr.Rip),
132132 else => error.InvalidRegister,
133133 },
134 .aarch64 => switch (reg_number) {
134 .aarch64, .aarch64_be => switch (reg_number) {
135135 0...30 => mem.asBytes(&thread_context_ptr.DUMMYUNIONNAME.X[reg_number]),
136136 31 => mem.asBytes(&thread_context_ptr.Sp),
137137 32 => mem.asBytes(&thread_context_ptr.Pc),
......@@ -269,7 +269,7 @@ pub fn regBytes(
269269 },
270270 else => error.UnimplementedOs,
271271 },
272 .arm => switch (builtin.os.tag) {
272 .arm, .armeb, .thumb, .thumbeb => switch (builtin.os.tag) {
273273 .linux => switch (reg_number) {
274274 0 => mem.asBytes(&ucontext_ptr.mcontext.arm_r0),
275275 1 => mem.asBytes(&ucontext_ptr.mcontext.arm_r1),
......@@ -292,7 +292,7 @@ pub fn regBytes(
292292 },
293293 else => error.UnimplementedOs,
294294 },
295 .aarch64 => switch (builtin.os.tag) {
295 .aarch64, .aarch64_be => switch (builtin.os.tag) {
296296 .macos, .ios, .watchos => switch (reg_number) {
297297 0...28 => mem.asBytes(&ucontext_ptr.mcontext.ss.regs[reg_number]),
298298 29 => mem.asBytes(&ucontext_ptr.mcontext.ss.fp),
lib/std/debug/SelfInfo.zig+5-5
......@@ -1419,7 +1419,7 @@ pub fn unwindFrameMachO(
14191419 return unwindFrameMachODwarf(context, ma, eh_frame orelse return error.MissingEhFrame, @intCast(encoding.value.x86_64.dwarf));
14201420 },
14211421 },
1422 .aarch64 => switch (encoding.mode.arm64) {
1422 .aarch64, .aarch64_be => switch (encoding.mode.arm64) {
14231423 .OLD => return error.UnimplementedUnwindEncoding,
14241424 .FRAMELESS => blk: {
14251425 const sp = (try regValueNative(context.thread_context, spRegNum(reg_context), reg_context)).*;
......@@ -1535,7 +1535,7 @@ pub const UnwindContext = struct {
15351535/// Some platforms use pointer authentication - the upper bits of instruction pointers contain a signature.
15361536/// This function clears these signature bits to make the pointer usable.
15371537pub inline fn stripInstructionPtrAuthCode(ptr: usize) usize {
1538 if (native_arch == .aarch64) {
1538 if (native_arch.isAARCH64()) {
15391539 // `hint 0x07` maps to `xpaclri` (or `nop` if the hardware doesn't support it)
15401540 // The save / restore is because `xpaclri` operates on x30 (LR)
15411541 return asm (
......@@ -1787,11 +1787,11 @@ pub fn supportsUnwinding(target: std.Target) bool {
17871787 .linux, .netbsd, .freebsd, .openbsd, .macos, .ios, .solaris, .illumos => true,
17881788 else => false,
17891789 },
1790 .arm => switch (target.os.tag) {
1790 .arm, .armeb, .thumb, .thumbeb => switch (target.os.tag) {
17911791 .linux => true,
17921792 else => false,
17931793 },
1794 .aarch64 => switch (target.os.tag) {
1794 .aarch64, .aarch64_be => switch (target.os.tag) {
17951795 .linux, .netbsd, .freebsd, .macos, .ios => true,
17961796 else => false,
17971797 },
......@@ -2194,7 +2194,7 @@ pub const VirtualMachine = struct {
21942194/// the .undefined rule by default, but allows ABI authors to override that.
21952195fn getRegDefaultValue(reg_number: u8, context: *UnwindContext, out: []u8) !void {
21962196 switch (builtin.cpu.arch) {
2197 .aarch64 => {
2197 .aarch64, .aarch64_be => {
21982198 // Callee-saved registers are initialized as if they had the .same_value rule
21992199 if (reg_number >= 19 and reg_number <= 28) {
22002200 const src = try regBytes(context.thread_context, reg_number, context.reg_context);
lib/std/simd.zig+1
......@@ -462,6 +462,7 @@ pub fn prefixScan(comptime op: std.builtin.ReduceOp, comptime hop: isize, vec: a
462462
463463test "vector prefix scan" {
464464 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest;
465 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21893
465466
466467 if (comptime builtin.cpu.arch.isMIPS()) {
467468 return error.SkipZigTest;
test/behavior/atomics.zig+2-1
......@@ -5,7 +5,8 @@ const expectEqual = std.testing.expectEqual;
55
66const supports_128_bit_atomics = switch (builtin.cpu.arch) {
77 // TODO: Ideally this could be sync'd with the logic in Sema.
8 .aarch64, .aarch64_be => true,
8 .aarch64 => true,
9 .aarch64_be => false, // Fails due to LLVM issues.
910 .x86_64 => std.Target.x86.featureSetHas(builtin.cpu.features, .cx16),
1011 else => false,
1112};
test/behavior/bitcast.zig+1
......@@ -402,6 +402,7 @@ test "bitcast vector to integer and back" {
402402 if (builtin.zig_backend == .stage2_wasm) return error.SkipZigTest; // TODO
403403 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest;
404404 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
405 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
405406
406407 const arr: [16]bool = [_]bool{ true, false } ++ [_]bool{true} ** 14;
407408 var x: @Vector(16, bool) = @splat(true);
test/behavior/union.zig+1-3
......@@ -1820,10 +1820,8 @@ test "reinterpret packed union" {
18201820 try comptime S.doTheTest();
18211821
18221822 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
1823 if (builtin.cpu.arch.isPowerPC()) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21050
1824 if (builtin.cpu.arch.isMIPS()) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21050
18251823 if (builtin.cpu.arch.isWasm()) return error.SkipZigTest; // TODO
1826 if (builtin.cpu.arch == .s390x and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest; // TODO
1824 if (builtin.cpu.arch.endian() == .big) return error.SkipZigTest; // https://github.com/ziglang/zig/issues/21050
18271825 try S.doTheTest();
18281826}
18291827
test/behavior/vector.zig+7
......@@ -1060,6 +1060,7 @@ test "@addWithOverflow" {
10601060 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
10611061 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
10621062 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1063 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
10631064
10641065 const S = struct {
10651066 fn doTheTest() !void {
......@@ -1108,6 +1109,7 @@ test "@subWithOverflow" {
11081109 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
11091110 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
11101111 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1112 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
11111113
11121114 const S = struct {
11131115 fn doTheTest() !void {
......@@ -1140,6 +1142,7 @@ test "@mulWithOverflow" {
11401142 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
11411143 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
11421144 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1145 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
11431146
11441147 const S = struct {
11451148 fn doTheTest() !void {
......@@ -1162,6 +1165,7 @@ test "@shlWithOverflow" {
11621165 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
11631166 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
11641167 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1168 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
11651169
11661170 const S = struct {
11671171 fn doTheTest() !void {
......@@ -1245,6 +1249,7 @@ test "byte vector initialized in inline function" {
12451249 if (builtin.zig_backend == .stage2_arm) return error.SkipZigTest; // TODO
12461250 if (builtin.zig_backend == .stage2_sparc64) return error.SkipZigTest; // TODO
12471251 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1252 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
12481253
12491254 if (comptime builtin.zig_backend == .stage2_llvm and builtin.cpu.arch == .x86_64 and
12501255 builtin.cpu.features.isEnabled(@intFromEnum(std.Target.x86.Feature.avx512f)))
......@@ -1370,6 +1375,7 @@ test "store packed vector element" {
13701375 if (builtin.zig_backend == .stage2_x86_64) return error.SkipZigTest; // TODO
13711376 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
13721377 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1378 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
13731379
13741380 var v = @Vector(4, u1){ 1, 1, 1, 1 };
13751381 try expectEqual(@Vector(4, u1){ 1, 1, 1, 1 }, v);
......@@ -1406,6 +1412,7 @@ test "store vector with memset" {
14061412 if (builtin.zig_backend == .stage2_spirv64) return error.SkipZigTest; // TODO
14071413 if (builtin.zig_backend == .stage2_c) return error.SkipZigTest; // TODO
14081414 if (builtin.zig_backend == .stage2_riscv64) return error.SkipZigTest;
1415 if (builtin.cpu.arch == .aarch64_be and builtin.zig_backend == .stage2_llvm) return error.SkipZigTest;
14091416
14101417 var a: [5]@Vector(2, i1) = undefined;
14111418 var b: [5]@Vector(2, u2) = undefined;
test/llvm_targets.zig-3
......@@ -225,7 +225,6 @@ const targets = [_]std.Target.Query{
225225 .{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .gnu },
226226 .{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .musl },
227227 .{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .none },
228 .{ .cpu_arch = .riscv32, .os_tag = .linux, .abi = .ohos },
229228 .{ .cpu_arch = .riscv32, .os_tag = .rtems, .abi = .none },
230229 .{ .cpu_arch = .riscv32, .os_tag = .uefi, .abi = .none },
231230
......@@ -238,7 +237,6 @@ const targets = [_]std.Target.Query{
238237 .{ .cpu_arch = .riscv64, .os_tag = .linux, .abi = .gnu },
239238 .{ .cpu_arch = .riscv64, .os_tag = .linux, .abi = .musl },
240239 .{ .cpu_arch = .riscv64, .os_tag = .linux, .abi = .none },
241 .{ .cpu_arch = .riscv64, .os_tag = .linux, .abi = .ohos },
242240 .{ .cpu_arch = .riscv64, .os_tag = .netbsd, .abi = .none },
243241 .{ .cpu_arch = .riscv64, .os_tag = .openbsd, .abi = .none },
244242 .{ .cpu_arch = .riscv64, .os_tag = .rtems, .abi = .none },
......@@ -326,7 +324,6 @@ const targets = [_]std.Target.Query{
326324 .{ .cpu_arch = .x86, .os_tag = .linux, .abi = .gnu },
327325 .{ .cpu_arch = .x86, .os_tag = .linux, .abi = .musl },
328326 .{ .cpu_arch = .x86, .os_tag = .linux, .abi = .none },
329 .{ .cpu_arch = .x86, .os_tag = .linux, .abi = .ohos },
330327 .{ .cpu_arch = .x86, .os_tag = .netbsd, .abi = .none },
331328 .{ .cpu_arch = .x86, .os_tag = .openbsd, .abi = .none },
332329 .{ .cpu_arch = .x86, .os_tag = .rtems, .abi = .none },
test/tests.zig+24
......@@ -291,6 +291,30 @@ const test_targets = blk: {
291291 .link_libc = true,
292292 },
293293
294 .{
295 .target = .{
296 .cpu_arch = .aarch64_be,
297 .os_tag = .linux,
298 .abi = .none,
299 },
300 },
301 .{
302 .target = .{
303 .cpu_arch = .aarch64_be,
304 .os_tag = .linux,
305 .abi = .musl,
306 },
307 .link_libc = true,
308 },
309 .{
310 .target = .{
311 .cpu_arch = .aarch64_be,
312 .os_tag = .linux,
313 .abi = .gnu,
314 },
315 .link_libc = true,
316 },
317
294318 .{
295319 .target = .{
296320 .cpu_arch = .arm,