authorgravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-11-25 16:45:35+01:00
committergravatar for kubkon@jakubkonka.comJakub Konka <kubkon@jakubkonka.com> 2022-11-28 17:07:34+01:00
log625415d7388deea1ee2d95fe5bbed28bf6a52d01
tree4cb4b407e97f14bdf6799526fdca74da067bd7e2
parent1eac3c57eca2e736275d0d5066f0ff431ae1f9e8

windows: add zig impl of IsProcessorFeaturePresent syscall

1 files changed, 246 insertions(+), 70 deletions(-)

lib/std/os/windows.zig+246-70
...@@ -2103,6 +2103,7 @@ pub const USHORT = u16;...@@ -2103,6 +2103,7 @@ pub const USHORT = u16;
2103pub const SHORT = i16;2103pub const SHORT = i16;
2104pub const ULONG = u32;2104pub const ULONG = u32;
2105pub const LONG = i32;2105pub const LONG = i32;
2106pub const ULONG64 = u64;
2106pub const ULONGLONG = u64;2107pub const ULONGLONG = u64;
2107pub const LONGLONG = i64;2108pub const LONGLONG = i64;
2108pub const HLOCAL = HANDLE;2109pub const HLOCAL = HANDLE;
...@@ -3715,106 +3716,281 @@ pub const CTRL_SHUTDOWN_EVENT: DWORD = 6;...@@ -3715,106 +3716,281 @@ pub const CTRL_SHUTDOWN_EVENT: DWORD = 6;
37153716
3716pub const HANDLER_ROUTINE = std.meta.FnPtr(fn (dwCtrlType: DWORD) callconv(WINAPI) BOOL);3717pub const HANDLER_ROUTINE = std.meta.FnPtr(fn (dwCtrlType: DWORD) callconv(WINAPI) BOOL);
37173718
3718/// The 64-bit load/store atomic instructions are available.3719/// Processor feature enumeration.
3719pub const PF_ARM_64BIT_LOADSTORE_ATOMIC = 25;3720pub const PF = enum(DWORD) {
3721 /// On a Pentium, a floating-point precision error can occur in rare circumstances.
3722 FLOATING_POINT_PRECISION_ERRATA = 0,
37203723
3721/// The divide instruction_available.3724 /// Floating-point operations are emulated using software emulator.
3722pub const PF_ARM_DIVIDE_INSTRUCTION_AVAILABLE = 24;3725 /// This function returns a nonzero value if floating-point operations are emulated; otherwise, it returns zero.
3726 FLOATING_POINT_EMULATED = 1,
37233727
3724/// The external cache is available.3728 /// The atomic compare and exchange operation (cmpxchg) is available.
3725pub const PF_ARM_EXTERNAL_CACHE_AVAILABLE = 26;3729 COMPARE_EXCHANGE_DOUBLE = 2,
37263730
3727/// The floating-point multiply-accumulate instruction is available.3731 /// The MMX instruction set is available.
3728pub const PF_ARM_FMAC_INSTRUCTIONS_AVAILABLE = 27;3732 MMX_INSTRUCTIONS_AVAILABLE = 3,
37293733
3730/// The VFP/Neon: 32 x 64bit register bank is present.3734 /// The SSE instruction set is available.
3731/// This flag has the same meaning as PF_ARM_VFP_EXTENDED_REGISTERS.3735 XMMI_INSTRUCTIONS_AVAILABLE = 6,
3732pub const PF_ARM_VFP_32_REGISTERS_AVAILABLE = 18;
37333736
3734/// The 3D-Now instruction is available.3737 /// The 3D-Now instruction is available.
3735pub const PF_3DNOW_INSTRUCTIONS_AVAILABLE = 7;3738 @"3DNOW_INSTRUCTIONS_AVAILABLE" = 7,
37363739
3737/// The processor channels are enabled.3740 /// The RDTSC instruction is available.
3738pub const PF_CHANNELS_ENABLED = 16;3741 RDTSC_INSTRUCTION_AVAILABLE = 8,
37393742
3740/// The atomic compare and exchange operation (cmpxchg) is available.3743 /// The processor is PAE-enabled.
3741pub const PF_COMPARE_EXCHANGE_DOUBLE = 2;3744 PAE_ENABLED = 9,
37423745
3743/// The atomic compare and exchange 128-bit operation (cmpxchg16b) is available.3746 /// The SSE2 instruction set is available.
3744pub const PF_COMPARE_EXCHANGE128 = 14;3747 XMMI64_INSTRUCTIONS_AVAILABLE = 10,
37453748
3746/// The atomic compare 64 and exchange 128-bit operation (cmp8xchg16) is available.3749 /// Data execution prevention is enabled.
3747pub const PF_COMPARE64_EXCHANGE128 = 15;3750 NX_ENABLED = 12,
37483751
3749/// _fastfail() is available.3752 /// The SSE3 instruction set is available.
3750pub const PF_FASTFAIL_AVAILABLE = 23;3753 SSE3_INSTRUCTIONS_AVAILABLE = 13,
37513754
3752/// Floating-point operations are emulated using software emulator.3755 /// The atomic compare and exchange 128-bit operation (cmpxchg16b) is available.
3753/// This function returns a nonzero value if floating-point operations are emulated; otherwise, it returns zero.3756 COMPARE_EXCHANGE128 = 14,
3754pub const PF_FLOATING_POINT_EMULATED = 1;
37553757
3756/// On a Pentium, a floating-point precision error can occur in rare circumstances.3758 /// The atomic compare 64 and exchange 128-bit operation (cmp8xchg16) is available.
3757pub const PF_FLOATING_POINT_PRECISION_ERRATA = 0;3759 COMPARE64_EXCHANGE128 = 15,
37583760
3759/// The MMX instruction set is available.3761 /// The processor channels are enabled.
3760pub const PF_MMX_INSTRUCTIONS_AVAILABLE = 3;3762 CHANNELS_ENABLED = 16,
37613763
3762/// Data execution prevention is enabled.3764 /// The processor implements the XSAVI and XRSTOR instructions.
3763pub const PF_NX_ENABLED = 12;3765 XSAVE_ENABLED = 17,
37643766
3765/// The processor is PAE-enabled.3767 /// The VFP/Neon: 32 x 64bit register bank is present.
3766pub const PF_PAE_ENABLED = 9;3768 /// This flag has the same meaning as PF_ARM_VFP_EXTENDED_REGISTERS.
3769 ARM_VFP_32_REGISTERS_AVAILABLE = 18,
37673770
3768/// The RDTSC instruction is available.3771 /// Second Level Address Translation is supported by the hardware.
3769pub const PF_RDTSC_INSTRUCTION_AVAILABLE = 8;3772 SECOND_LEVEL_ADDRESS_TRANSLATION = 20,
37703773
3771/// RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE instructions are available.3774 /// Virtualization is enabled in the firmware and made available by the operating system.
3772pub const PF_RDWRFSGBASE_AVAILABLE = 22;3775 VIRT_FIRMWARE_ENABLED = 21,
37733776
3774/// Second Level Address Translation is supported by the hardware.3777 /// RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE instructions are available.
3775pub const PF_SECOND_LEVEL_ADDRESS_TRANSLATION = 20;3778 RDWRFSGBASE_AVAILABLE = 22,
37763779
3777/// The SSE3 instruction set is available.3780 /// _fastfail() is available.
3778pub const PF_SSE3_INSTRUCTIONS_AVAILABLE = 13;3781 FASTFAIL_AVAILABLE = 23,
37793782
3780/// The SSSE3 instruction set is available.3783 /// The divide instruction_available.
3781pub const PF_SSSE3_INSTRUCTIONS_AVAILABLE = 36;3784 ARM_DIVIDE_INSTRUCTION_AVAILABLE = 24,
37823785
3783/// The SSE4_1 instruction set is available.3786 /// The 64-bit load/store atomic instructions are available.
3784pub const PF_SSE4_1_INSTRUCTIONS_AVAILABLE = 37;3787 ARM_64BIT_LOADSTORE_ATOMIC = 25,
37853788
3786/// The SSE4_2 instruction set is available.3789 /// The external cache is available.
3787pub const PF_SSE4_2_INSTRUCTIONS_AVAILABLE = 38;3790 ARM_EXTERNAL_CACHE_AVAILABLE = 26,
37883791
3789/// The AVX instruction set is available.3792 /// The floating-point multiply-accumulate instruction is available.
3790pub const PF_AVX_INSTRUCTIONS_AVAILABLE = 39;3793 ARM_FMAC_INSTRUCTIONS_AVAILABLE = 27,
37913794
3792/// The AVX2 instruction set is available.3795 /// This ARM processor implements the ARM v8 instructions set.
3793pub const PF_AVX2_INSTRUCTIONS_AVAILABLE = 40;3796 ARM_V8_INSTRUCTIONS_AVAILABLE = 29,
37943797
3795/// The AVX512F instruction set is available.3798 /// This ARM processor implements the ARM v8 extra cryptographic instructions (i.e., AES, SHA1 and SHA2).
3796pub const PF_AVX512F_INSTRUCTIONS_AVAILABLE = 41;3799 ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE = 30,
37973800
3798/// Virtualization is enabled in the firmware and made available by the operating system.3801 /// This ARM processor implements the ARM v8 extra CRC32 instructions.
3799pub const PF_VIRT_FIRMWARE_ENABLED = 21;3802 ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE = 31,
38003803
3801/// The SSE instruction set is available.3804 /// This ARM processor implements the ARM v8.1 atomic instructions (e.g., CAS, SWP).
3802pub const PF_XMMI_INSTRUCTIONS_AVAILABLE = 6;3805 ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE = 34,
38033806
3804/// The SSE2 instruction set is available.3807 /// The SSSE3 instruction set is available.
3805pub const PF_XMMI64_INSTRUCTIONS_AVAILABLE = 10;3808 SSSE3_INSTRUCTIONS_AVAILABLE = 36,
38063809
3807/// The processor implements the XSAVI and XRSTOR instructions.3810 /// The SSE4_1 instruction set is available.
3808pub const PF_XSAVE_ENABLED = 17;3811 SSE4_1_INSTRUCTIONS_AVAILABLE = 37,
38093812
3810/// This ARM processor implements the ARM v8 instructions set.3813 /// The SSE4_2 instruction set is available.
3811pub const PF_ARM_V8_INSTRUCTIONS_AVAILABLE = 29;3814 SSE4_2_INSTRUCTIONS_AVAILABLE = 38,
38123815
3813/// This ARM processor implements the ARM v8 extra cryptographic instructions (i.e., AES, SHA1 and SHA2).3816 /// The AVX instruction set is available.
3814pub const PF_ARM_V8_CRYPTO_INSTRUCTIONS_AVAILABLE = 30;3817 AVX_INSTRUCTIONS_AVAILABLE = 39,
38153818
3816/// This ARM processor implements the ARM v8 extra CRC32 instructions.3819 /// The AVX2 instruction set is available.
3817pub const PF_ARM_V8_CRC32_INSTRUCTIONS_AVAILABLE = 31;3820 AVX2_INSTRUCTIONS_AVAILABLE = 40,
38183821
3819/// This ARM processor implements the ARM v8.1 atomic instructions (e.g., CAS, SWP).3822 /// The AVX512F instruction set is available.
3820pub const PF_ARM_V81_ATOMIC_INSTRUCTIONS_AVAILABLE = 34;3823 AVX512F_INSTRUCTIONS_AVAILABLE = 41,
3824};
3825
3826pub const MAX_WOW64_SHARED_ENTRIES = 16;
3827pub const PROCESSOR_FEATURE_MAX = 64;
3828pub const MAXIMUM_XSTATE_FEATURES = 64;
3829
3830pub const KSYSTEM_TIME = extern struct {
3831 LowPart: ULONG,
3832 High1Time: LONG,
3833 High2Time: LONG,
3834};
3835
3836pub const NT_PRODUCT_TYPE = enum(INT) {
3837 NtProductWinNt = 1,
3838 NtProductLanManNt,
3839 NtProductServer,
3840};
3841
3842pub const ALTERNATIVE_ARCHITECTURE_TYPE = enum(INT) {
3843 StandardDesign,
3844 NEC98x86,
3845 EndAlternatives,
3846};
3847
3848pub const XSTATE_FEATURE = extern struct {
3849 Offset: ULONG,
3850 Size: ULONG,
3851};
3852
3853pub const XSTATE_CONFIGURATION = extern struct {
3854 EnabledFeatures: ULONG64,
3855 Size: ULONG,
3856 OptimizedSave: ULONG,
3857 Features: [MAXIMUM_XSTATE_FEATURES]XSTATE_FEATURE,
3858};
3859
3860/// Shared Kernel User Data
3861pub const KUSER_SHARED_DATA = extern struct {
3862 TickCountLowDeprecated: ULONG,
3863 TickCountMultiplier: ULONG,
3864 InterruptTime: KSYSTEM_TIME,
3865 SystemTime: KSYSTEM_TIME,
3866 TimeZoneBias: KSYSTEM_TIME,
3867 ImageNumberLow: USHORT,
3868 ImageNumberHigh: USHORT,
3869 NtSystemRoot: [260]WCHAR,
3870 MaxStackTraceDepth: ULONG,
3871 CryptoExponent: ULONG,
3872 TimeZoneId: ULONG,
3873 LargePageMinimum: ULONG,
3874 AitSamplingValue: ULONG,
3875 AppCompatFlag: ULONG,
3876 RNGSeedVersion: ULONGLONG,
3877 GlobalValidationRunlevel: ULONG,
3878 TimeZoneBiasStamp: LONG,
3879 NtBuildNumber: ULONG,
3880 NtProductType: NT_PRODUCT_TYPE,
3881 ProductTypeIsValid: BOOLEAN,
3882 Reserved0: [1]BOOLEAN,
3883 NativeProcessorArchitecture: USHORT,
3884 NtMajorVersion: ULONG,
3885 NtMinorVersion: ULONG,
3886 ProcessorFeatures: [PROCESSOR_FEATURE_MAX]BOOLEAN,
3887 Reserved1: ULONG,
3888 Reserved3: ULONG,
3889 TimeSlip: ULONG,
3890 AlternativeArchitecture: ALTERNATIVE_ARCHITECTURE_TYPE,
3891 BootId: ULONG,
3892 SystemExpirationDate: LARGE_INTEGER,
3893 SuiteMaskY: ULONG,
3894 KdDebuggerEnabled: BOOLEAN,
3895 DummyUnion1: extern union {
3896 MitigationPolicies: UCHAR,
3897 Alt: packed struct {
3898 NXSupportPolicy: u2,
3899 SEHValidationPolicy: u2,
3900 CurDirDevicesSkippedForDlls: u2,
3901 Reserved: u2,
3902 },
3903 },
3904 CyclesPerYield: USHORT,
3905 ActiveConsoleId: ULONG,
3906 DismountCount: ULONG,
3907 ComPlusPackage: ULONG,
3908 LastSystemRITEventTickCount: ULONG,
3909 NumberOfPhysicalPages: ULONG,
3910 SafeBootMode: BOOLEAN,
3911 DummyUnion2: extern union {
3912 VirtualizationFlags: UCHAR,
3913 Alt: packed struct {
3914 ArchStartedInEl2: u1,
3915 QcSlIsSupported: u1,
3916 SpareBits: u6,
3917 },
3918 },
3919 Reserved12: [2]UCHAR,
3920 DummyUnion3: extern union {
3921 SharedDataFlags: ULONG,
3922 Alt: packed struct {
3923 DbgErrorPortPresent: u1,
3924 DbgElevationEnabled: u1,
3925 DbgVirtEnabled: u1,
3926 DbgInstallerDetectEnabled: u1,
3927 DbgLkgEnabled: u1,
3928 DbgDynProcessorEnabled: u1,
3929 DbgConsoleBrokerEnabled: u1,
3930 DbgSecureBootEnabled: u1,
3931 DbgMultiSessionSku: u1,
3932 DbgMultiUsersInSessionSku: u1,
3933 DbgStateSeparationEnabled: u1,
3934 SpareBits: u21,
3935 },
3936 },
3937 DataFlagsPad: [1]ULONG,
3938 TestRetInstruction: ULONGLONG,
3939 QpcFrequency: LONGLONG,
3940 SystemCall: ULONG,
3941 Reserved2: ULONG,
3942 SystemCallPad: [2]ULONGLONG,
3943 DummyUnion4: extern union {
3944 TickCount: KSYSTEM_TIME,
3945 TickCountQuad: ULONG64,
3946 Alt: extern struct {
3947 ReservedTickCountOverlay: [3]ULONG,
3948 TickCountPad: [1]ULONG,
3949 },
3950 },
3951 Cookie: ULONG,
3952 CookiePad: [1]ULONG,
3953 ConsoleSessionForegroundProcessId: LONGLONG,
3954 TimeUpdateLock: ULONGLONG,
3955 BaselineSystemTimeQpc: ULONGLONG,
3956 BaselineInterruptTimeQpc: ULONGLONG,
3957 QpcSystemTimeIncrement: ULONGLONG,
3958 QpcInterruptTimeIncrement: ULONGLONG,
3959 QpcSystemTimeIncrementShift: UCHAR,
3960 QpcInterruptTimeIncrementShift: UCHAR,
3961 UnparkedProcessorCount: USHORT,
3962 EnclaveFeatureMask: [4]ULONG,
3963 TelemetryCoverageRound: ULONG,
3964 UserModeGlobalLogger: [16]USHORT,
3965 ImageFileExecutionOptions: ULONG,
3966 LangGenerationCount: ULONG,
3967 Reserved4: ULONGLONG,
3968 InterruptTimeBias: ULONGLONG,
3969 QpcBias: ULONGLONG,
3970 ActiveProcessorCount: ULONG,
3971 ActiveGroupCount: UCHAR,
3972 Reserved9: UCHAR,
3973 DummyUnion5: extern union {
3974 QpcData: USHORT,
3975 Alt: extern struct {
3976 QpcBypassEnabled: UCHAR,
3977 QpcShift: UCHAR,
3978 },
3979 },
3980 TimeZoneBiasEffectiveStart: LARGE_INTEGER,
3981 TimeZoneBiasEffectiveEnd: LARGE_INTEGER,
3982 XState: XSTATE_CONFIGURATION,
3983 FeatureConfigurationChangeStamp: KSYSTEM_TIME,
3984 Spare: ULONG,
3985 UserPointerAuthMask: ULONG64,
3986};
3987
3988/// Read-only user-mode address for the shared data.
3989/// https://www.geoffchappell.com/studies/windows/km/ntoskrnl/inc/api/ntexapi_x/kuser_shared_data/index.htm
3990/// https://msrc-blog.microsoft.com/2022/04/05/randomizing-the-kuser_shared_data-structure-on-windows/
3991pub const SharedUserData: *const KUSER_SHARED_DATA = @intToPtr(*const KUSER_SHARED_DATA, 0x7FFE0000);
3992
3993pub fn IsProcessorFeaturePresent(feature: PF) bool {
3994 if (@enumToInt(feature) >= PROCESSOR_FEATURE_MAX) return false;
3995 return SharedUserData.ProcessorFeatures[@enumToInt(feature)] == 1;
3996}