authorgravatar for robin@voetter.nlRobin Voetter <robin@voetter.nl> 2022-08-06 18:22:56+02:00
committergravatar for robin@voetter.nlRobin Voetter <robin@voetter.nl> 2022-10-12 20:34:41+02:00
log6b69dcfdd28145791da43979474fec29a13e24d0
tree35417291ba915132c681149fef4ca20094951ffb
parent5dd3d17c201f83b853fa1f1bf5e459fb1582c3cf
signaturelock-open Commit is signed but in an unrecognized format.

amdgpu: add AmdgpuKernel calling convention

7 files changed, 27 insertions(+), 6 deletions(-)

lib/std/builtin.zig+1
...@@ -157,6 +157,7 @@ pub const CallingConvention = enum {...@@ -157,6 +157,7 @@ pub const CallingConvention = enum {
157 SysV,157 SysV,
158 Win64,158 Win64,
159 PtxKernel,159 PtxKernel,
160 AmdgpuKernel,
160};161};
161162
162/// This data structure is used by the Zig language code generation and163/// This data structure is used by the Zig language code generation and
src/Sema.zig+4
...@@ -8141,6 +8141,10 @@ fn funcCommon(...@@ -8141,6 +8141,10 @@ fn funcCommon(
8141 .nvptx, .nvptx64 => null,8141 .nvptx, .nvptx64 => null,
8142 else => @as([]const u8, "nvptx and nvptx64"),8142 else => @as([]const u8, "nvptx and nvptx64"),
8143 },8143 },
8144 .AmdgpuKernel => switch (arch) {
8145 .amdgcn => null,
8146 else => @as([]const u8, "amdgcn"),
8147 },
8144 }) |allowed_platform| {8148 }) |allowed_platform| {
8145 return sema.fail(block, cc_src, "callconv '{s}' is only available on {s}, not {s}", .{8149 return sema.fail(block, cc_src, "callconv '{s}' is only available on {s}, not {s}", .{
8146 @tagName(cc_workaround),8150 @tagName(cc_workaround),
src/codegen/llvm.zig+5-1
...@@ -4425,7 +4425,7 @@ pub const FuncGen = struct {...@@ -4425,7 +4425,7 @@ pub const FuncGen = struct {
4425 .cmp_lt => try self.airCmp(inst, .lt, false),4425 .cmp_lt => try self.airCmp(inst, .lt, false),
4426 .cmp_lte => try self.airCmp(inst, .lte, false),4426 .cmp_lte => try self.airCmp(inst, .lte, false),
4427 .cmp_neq => try self.airCmp(inst, .neq, false),4427 .cmp_neq => try self.airCmp(inst, .neq, false),
4428 4428
4429 .cmp_eq_optimized => try self.airCmp(inst, .eq, true),4429 .cmp_eq_optimized => try self.airCmp(inst, .eq, true),
4430 .cmp_gt_optimized => try self.airCmp(inst, .gt, true),4430 .cmp_gt_optimized => try self.airCmp(inst, .gt, true),
4431 .cmp_gte_optimized => try self.airCmp(inst, .gte, true),4431 .cmp_gte_optimized => try self.airCmp(inst, .gte, true),
...@@ -9807,6 +9807,10 @@ fn toLlvmCallConv(cc: std.builtin.CallingConvention, target: std.Target) llvm.Ca...@@ -9807,6 +9807,10 @@ fn toLlvmCallConv(cc: std.builtin.CallingConvention, target: std.Target) llvm.Ca
9807 .nvptx, .nvptx64 => .PTX_Kernel,9807 .nvptx, .nvptx64 => .PTX_Kernel,
9808 else => unreachable,9808 else => unreachable,
9809 },9809 },
9810 .AmdgpuKernel => return switch (target.cpu.arch) {
9811 .amdgcn => .AMDGPU_KERNEL,
9812 else => unreachable,
9813 },
9810 };9814 };
9811}9815}
98129816
src/stage1/all_types.hpp+2-1
...@@ -85,7 +85,8 @@ enum CallingConvention {...@@ -85,7 +85,8 @@ enum CallingConvention {
85 CallingConventionAAPCSVFP,85 CallingConventionAAPCSVFP,
86 CallingConventionSysV,86 CallingConventionSysV,
87 CallingConventionWin64,87 CallingConventionWin64,
88 CallingConventionPtxKernel88 CallingConventionPtxKernel,
89 CallingConventionAmdgpuKernel
89};90};
9091
91// Stage 1 supports only the generic address space92// Stage 1 supports only the generic address space
src/stage1/analyze.cpp+9-3
...@@ -993,6 +993,7 @@ const char *calling_convention_name(CallingConvention cc) {...@@ -993,6 +993,7 @@ const char *calling_convention_name(CallingConvention cc) {
993 case CallingConventionSysV: return "SysV";993 case CallingConventionSysV: return "SysV";
994 case CallingConventionWin64: return "Win64";994 case CallingConventionWin64: return "Win64";
995 case CallingConventionPtxKernel: return "PtxKernel";995 case CallingConventionPtxKernel: return "PtxKernel";
996 case CallingConventionAmdgpuKernel: return "AmdgpuKernel";
996 }997 }
997 zig_unreachable();998 zig_unreachable();
998}999}
...@@ -1017,6 +1018,7 @@ bool calling_convention_allows_zig_types(CallingConvention cc) {...@@ -1017,6 +1018,7 @@ bool calling_convention_allows_zig_types(CallingConvention cc) {
1017 case CallingConventionAAPCSVFP:1018 case CallingConventionAAPCSVFP:
1018 case CallingConventionSysV:1019 case CallingConventionSysV:
1019 case CallingConventionWin64:1020 case CallingConventionWin64:
1021 case CallingConventionAmdgpuKernel:
1020 return false;1022 return false;
1021 }1023 }
1022 zig_unreachable();1024 zig_unreachable();
...@@ -2019,6 +2021,9 @@ Error emit_error_unless_callconv_allowed_for_target(CodeGen *g, AstNode *source_...@@ -2019,6 +2021,9 @@ Error emit_error_unless_callconv_allowed_for_target(CodeGen *g, AstNode *source_
2019 allowed_platforms = "nvptx and nvptx64";2021 allowed_platforms = "nvptx and nvptx64";
2020 }2022 }
2021 break;2023 break;
2024 case CallingConventionAmdgpuKernel:
2025 if (g->zig_target->arch != ZigLLVM_amdgcn)
2026 allowed_platforms = "amdgcn and amdpal";
20222027
2023 }2028 }
2024 if (allowed_platforms != nullptr) {2029 if (allowed_platforms != nullptr) {
...@@ -3857,6 +3862,7 @@ static void resolve_decl_fn(CodeGen *g, TldFn *tld_fn) {...@@ -3857,6 +3862,7 @@ static void resolve_decl_fn(CodeGen *g, TldFn *tld_fn) {
3857 case CallingConventionSysV:3862 case CallingConventionSysV:
3858 case CallingConventionWin64:3863 case CallingConventionWin64:
3859 case CallingConventionPtxKernel:3864 case CallingConventionPtxKernel:
3865 case CallingConventionAmdgpuKernel:
3860 add_fn_export(g, fn_table_entry, buf_ptr(&fn_table_entry->symbol_name),3866 add_fn_export(g, fn_table_entry, buf_ptr(&fn_table_entry->symbol_name),
3861 GlobalLinkageIdStrong, fn_cc);3867 GlobalLinkageIdStrong, fn_cc);
3862 break;3868 break;
...@@ -6012,7 +6018,7 @@ Error type_has_bits2(CodeGen *g, ZigType *type_entry, bool *result) {...@@ -6012,7 +6018,7 @@ Error type_has_bits2(CodeGen *g, ZigType *type_entry, bool *result) {
60126018
6013bool fn_returns_c_abi_small_struct(FnTypeId *fn_type_id) {6019bool fn_returns_c_abi_small_struct(FnTypeId *fn_type_id) {
6014 ZigType *type = fn_type_id->return_type;6020 ZigType *type = fn_type_id->return_type;
6015 return !calling_convention_allows_zig_types(fn_type_id->cc) && 6021 return !calling_convention_allows_zig_types(fn_type_id->cc) &&
6016 type->id == ZigTypeIdStruct && type->abi_size <= 16;6022 type->id == ZigTypeIdStruct && type->abi_size <= 16;
6017}6023}
60186024
...@@ -8698,7 +8704,7 @@ static LLVMTypeRef llvm_int_for_size(size_t size) {...@@ -8698,7 +8704,7 @@ static LLVMTypeRef llvm_int_for_size(size_t size) {
8698static LLVMTypeRef llvm_sse_for_size(size_t size) {8704static LLVMTypeRef llvm_sse_for_size(size_t size) {
8699 if (size > 4)8705 if (size > 4)
8700 return LLVMDoubleType();8706 return LLVMDoubleType();
8701 else 8707 else
8702 return LLVMFloatType();8708 return LLVMFloatType();
8703}8709}
87048710
...@@ -8756,7 +8762,7 @@ static Error resolve_llvm_c_abi_type(CodeGen *g, ZigType *ty) {...@@ -8756,7 +8762,7 @@ static Error resolve_llvm_c_abi_type(CodeGen *g, ZigType *ty) {
87568762
8757 LLVMTypeRef return_elem_types[] = {8763 LLVMTypeRef return_elem_types[] = {
8758 LLVMVoidType(),8764 LLVMVoidType(),
8759 LLVMVoidType(), 8765 LLVMVoidType(),
8760 };8766 };
8761 for (uint32_t i = 0; i <= eightbyte_index; i += 1) {8767 for (uint32_t i = 0; i <= eightbyte_index; i += 1) {
8762 if (type_classes[i] == X64CABIClass_INTEGER) {8768 if (type_classes[i] == X64CABIClass_INTEGER) {
src/stage1/codegen.cpp+5-1
...@@ -216,6 +216,9 @@ static ZigLLVM_CallingConv get_llvm_cc(CodeGen *g, CallingConvention cc) {...@@ -216,6 +216,9 @@ static ZigLLVM_CallingConv get_llvm_cc(CodeGen *g, CallingConvention cc) {
216 assert(g->zig_target->arch == ZigLLVM_nvptx ||216 assert(g->zig_target->arch == ZigLLVM_nvptx ||
217 g->zig_target->arch == ZigLLVM_nvptx64);217 g->zig_target->arch == ZigLLVM_nvptx64);
218 return ZigLLVM_PTX_Kernel;218 return ZigLLVM_PTX_Kernel;
219 case CallingConventionAmdgpuKernel:
220 assert(g->zig_target->arch == ZigLLVM_amdgcn);
221 return ZigLLVM_AMDGPU_KERNEL;
219222
220 }223 }
221 zig_unreachable();224 zig_unreachable();
...@@ -364,6 +367,7 @@ static bool cc_want_sret_attr(CallingConvention cc) {...@@ -364,6 +367,7 @@ static bool cc_want_sret_attr(CallingConvention cc) {
364 case CallingConventionSysV:367 case CallingConventionSysV:
365 case CallingConventionWin64:368 case CallingConventionWin64:
366 case CallingConventionPtxKernel:369 case CallingConventionPtxKernel:
370 case CallingConventionAmdgpuKernel:
367 return true;371 return true;
368 case CallingConventionAsync:372 case CallingConventionAsync:
369 case CallingConventionUnspecified:373 case CallingConventionUnspecified:
...@@ -3515,7 +3519,7 @@ static LLVMValueRef gen_soft_float_to_int_op(CodeGen *g, LLVMValueRef value_ref,...@@ -3515,7 +3519,7 @@ static LLVMValueRef gen_soft_float_to_int_op(CodeGen *g, LLVMValueRef value_ref,
35153519
3516 // Handle integers of non-pot bitsize by shortening them on the output3520 // Handle integers of non-pot bitsize by shortening them on the output
3517 if (result_type != wider_type) {3521 if (result_type != wider_type) {
3518 result = gen_widen_or_shorten(g, false, wider_type, result_type, result); 3522 result = gen_widen_or_shorten(g, false, wider_type, result_type, result);
3519 }3523 }
35203524
3521 return result;3525 return result;
src/stage1/ir.cpp+1
...@@ -11753,6 +11753,7 @@ static Stage1AirInst *ir_analyze_instruction_export(IrAnalyze *ira, Stage1ZirIns...@@ -11753,6 +11753,7 @@ static Stage1AirInst *ir_analyze_instruction_export(IrAnalyze *ira, Stage1ZirIns
11753 case CallingConventionSysV:11753 case CallingConventionSysV:
11754 case CallingConventionWin64:11754 case CallingConventionWin64:
11755 case CallingConventionPtxKernel:11755 case CallingConventionPtxKernel:
11756 case CallingConventionAmdgpuKernel:
11756 add_fn_export(ira->codegen, fn_entry, buf_ptr(symbol_name), global_linkage_id, cc);11757 add_fn_export(ira->codegen, fn_entry, buf_ptr(symbol_name), global_linkage_id, cc);
11757 fn_entry->section_name = section_name;11758 fn_entry->section_name = section_name;
11758 break;11759 break;