Commit 8f7cbaa4c0cebc22613a33d212569cf221d6a3df | zig

lib/compiler/aro/aro/Compilation.zig+2-2

...	...	@@ -363,7 +363,7 @@ fn generateSystemDefines(comp: *Compilation, w: anytype) !void {
363	363	\\#define __sparc_v9__ 1
364	364	\\
365	365	),
366		.sparc, .sparcel => try w.writeAll(
	366	.sparc => try w.writeAll(
367	367	\\#define __sparc__ 1
368	368	\\#define __sparc 1
369	369	\\
...	...	@@ -534,7 +534,7 @@ pub fn generateBuiltinMacros(comp: *Compilation, system_defines_mode: SystemDefi
534	534
535	535	if (system_defines_mode == .include_system_defines) {
536	536	try buf.appendSlice(
537		\\#define __VERSION__ "Aro
	537	\\#define __VERSION__ "Aro
538	538	++ @import("../backend.zig").version_str ++ "\"\n" ++
539	539	\\#define __Aro__
540	540	\\

lib/compiler/aro/aro/Driver/GCCDetector.zig+1-1

...	...	@@ -376,7 +376,7 @@ fn collectLibDirsAndTriples(
376	376	biarch_libdirs.appendSliceAssumeCapacity(&RISCV32LibDirs);
377	377	biarch_triple_aliases.appendSliceAssumeCapacity(&RISCV32Triples);
378	378	},
379		.sparc, .sparcel => {
	379	.sparc => {
380	380	lib_dirs.appendSliceAssumeCapacity(&SPARCv8LibDirs);
381	381	triple_aliases.appendSliceAssumeCapacity(&SPARCv8Triples);
382	382	biarch_libdirs.appendSliceAssumeCapacity(&SPARCv9LibDirs);

lib/compiler/aro/aro/target.zig+3-15

...	...	@@ -53,13 +53,12 @@ pub fn intPtrType(target: std.Target) Type {
53	53	.xcore,
54	54	.hexagon,
55	55	.m68k,
56		.spir,
57	56	.spirv32,
58	57	.arc,
59	58	.avr,
60	59	=> return .{ .specifier = .int },
61	60
62		.sparc, .sparcel => switch (target.os.tag) {
	61	.sparc => switch (target.os.tag) {
63	62	.netbsd, .openbsd => {},
64	63	else => return .{ .specifier = .int },
65	64	},
...	...	@@ -133,7 +132,7 @@ pub fn defaultFunctionAlignment(target: std.Target) u8 {
133	132	return switch (target.cpu.arch) {
134	133	.arm, .armeb => 4,
135	134	.aarch64, .aarch64_be => 4,
136		.sparc, .sparcel, .sparc64 => 4,
	135	.sparc, .sparc64 => 4,
137	136	.riscv64 => 2,
138	137	else => 1,
139	138	};
...	...	@@ -427,7 +426,7 @@ pub fn ldEmulationOption(target: std.Target, arm_endianness: ?std.builtin.Endian
427	426	.powerpc64le => "elf64lppc",
428	427	.riscv32 => "elf32lriscv",
429	428	.riscv64 => "elf64lriscv",
430		.sparc, .sparcel => "elf32_sparc",
	429	.sparc => "elf32_sparc",
431	430	.sparc64 => "elf64_sparc",
432	431	.loongarch32 => "elf32loongarch",
433	432	.loongarch64 => "elf64loongarch",
...	...	@@ -467,13 +466,11 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
467	466	.powerpcle,
468	467	.riscv32,
469	468	.sparc,
470		.sparcel,
471	469	.thumb,
472	470	.thumbeb,
473	471	.x86,
474	472	.xcore,
475	473	.nvptx,
476		.spir,
477	474	.kalimba,
478	475	.lanai,
479	476	.wasm32,
...	...	@@ -487,7 +484,6 @@ pub fn get32BitArchVariant(target: std.Target) ?std.Target {
487	484	.aarch64_be => copy.cpu.arch = .armeb,
488	485	.nvptx64 => copy.cpu.arch = .nvptx,
489	486	.wasm64 => copy.cpu.arch = .wasm32,
490		.spir64 => copy.cpu.arch = .spir,
491	487	.spirv64 => copy.cpu.arch = .spirv32,
492	488	.loongarch64 => copy.cpu.arch = .loongarch32,
493	489	.mips64 => copy.cpu.arch = .mips,
...	...	@@ -513,7 +509,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
513	509	.lanai,
514	510	.m68k,
515	511	.msp430,
516		.sparcel,
517	512	.spu_2,
518	513	.xcore,
519	514	.xtensa,
...	...	@@ -526,7 +521,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
526	521	.bpfel,
527	522	.nvptx64,
528	523	.wasm64,
529		.spir64,
530	524	.spirv64,
531	525	.loongarch64,
532	526	.mips64,
...	...	@@ -550,7 +544,6 @@ pub fn get64BitArchVariant(target: std.Target) ?std.Target {
550	544	.powerpcle => copy.cpu.arch = .powerpc64le,
551	545	.riscv32 => copy.cpu.arch = .riscv64,
552	546	.sparc => copy.cpu.arch = .sparc64,
553		.spir => copy.cpu.arch = .spir64,
554	547	.spirv32 => copy.cpu.arch = .spirv64,
555	548	.thumb => copy.cpu.arch = .aarch64,
556	549	.thumbeb => copy.cpu.arch = .aarch64_be,
...	...	@@ -597,7 +590,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
597	590	.riscv64 => "riscv64",
598	591	.sparc => "sparc",
599	592	.sparc64 => "sparc64",
600		.sparcel => "sparcel",
601	593	.s390x => "s390x",
602	594	.thumb => "thumb",
603	595	.thumbeb => "thumbeb",
...	...	@@ -607,8 +599,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
607	599	.xtensa => "xtensa",
608	600	.nvptx => "nvptx",
609	601	.nvptx64 => "nvptx64",
610		.spir => "spir",
611		.spir64 => "spir64",
612	602	.spirv32 => "spirv32",
613	603	.spirv64 => "spirv64",
614	604	.kalimba => "kalimba",
...	...	@@ -624,8 +614,6 @@ pub fn toLLVMTriple(target: std.Target, buf: []u8) []const u8 {
624	614
625	615	const llvm_os = switch (target.os.tag) {
626	616	.freestanding => "unknown",
627		.ananas => "ananas",
628		.cloudabi => "cloudabi",
629	617	.dragonfly => "dragonfly",
630	618	.freebsd => "freebsd",
631	619	.fuchsia => "fuchsia",

lib/compiler/aro/aro/toolchains/Linux.zig-1

...	...	@@ -357,7 +357,6 @@ fn getOSLibDir(target: std.Target) []const u8 {
357	357	.powerpc,
358	358	.powerpcle,
359	359	.sparc,
360		.sparcel,
361	360	=> return "lib32",
362	361	else => {},
363	362	}

lib/compiler_rt/atomics.zig+1-1

...	...	@@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) {
30	30	// On SPARC systems that lacks CAS and/or swap instructions, the only
31	31	// available atomic operation is a test-and-set (`ldstub`), so we force
32	32	// every atomic memory access to go through the lock.
33		.sparc, .sparcel => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
	33	.sparc => if (cpu.features.featureSetHas(.hasleoncasa)) @sizeOf(usize) else 0,
34	34
35	35	// XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
36	36	// and set this parameter accordingly.

lib/compiler_rt/clear_cache.zig+1-1

...	...	@@ -41,7 +41,7 @@ fn clear_cache(start: usize, end: usize) callconv(.C) void {
41	41	else => false,
42	42	};
43	43	const sparc = switch (arch) {
44		.sparc, .sparc64, .sparcel => true,
	44	.sparc, .sparc64 => true,
45	45	else => false,
46	46	};
47	47	const apple = switch (os) {

lib/std/Target.zig+12-48

...	...	@@ -17,8 +17,6 @@ pub const Os = struct {
17	17
18	18	pub const Tag = enum {
19	19	freestanding,
20		ananas,
21		cloudabi,
22	20	dragonfly,
23	21	freebsd,
24	22	fuchsia,
...	...	@@ -140,8 +138,6 @@ pub const Os = struct {
140	138	pub inline fn getVersionRangeTag(tag: Tag) @typeInfo(TaggedVersionRange).Union.tag_type.? {
141	139	return switch (tag) {
142	140	.freestanding,
143		.ananas,
144		.cloudabi,
145	141	.fuchsia,
146	142	.ps3,
147	143	.zos,
...	...	@@ -202,7 +198,7 @@ pub const Os = struct {
202	198	.mips, .mipsel, .mips64, .mips64el => "mips",
203	199	.powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
204	200	.riscv32, .riscv64 => "riscv",
205		.sparc, .sparcel, .sparc64 => "sparc",
	201	.sparc, .sparc64 => "sparc",
206	202	.x86, .x86_64 => "x86",
207	203	else => @tagName(arch),
208	204	},
...	...	@@ -373,8 +369,6 @@ pub const Os = struct {
373	369	pub fn default(tag: Tag, arch: Cpu.Arch) VersionRange {
374	370	return switch (tag) {
375	371	.freestanding,
376		.ananas,
377		.cloudabi,
378	372	.fuchsia,
379	373	.ps3,
380	374	.zos,
...	...	@@ -560,8 +554,6 @@ pub const Os = struct {
560	554	.linux,
561	555	.windows,
562	556	.freestanding,
563		.ananas,
564		.cloudabi,
565	557	.fuchsia,
566	558	.ps3,
567	559	.zos,
...	...	@@ -667,8 +659,6 @@ pub const Abi = enum {
667	659	pub fn default(arch: Cpu.Arch, os: Os) Abi {
668	660	return if (arch.isWasm()) .musl else switch (os.tag) {
669	661	.freestanding,
670		.ananas,
671		.cloudabi,
672	662	.dragonfly,
673	663	.ps3,
674	664	.zos,
...	...	@@ -1018,7 +1008,6 @@ pub const Cpu = struct {
1018	1008	riscv64,
1019	1009	sparc,
1020	1010	sparc64,
1021		sparcel,
1022	1011	s390x,
1023	1012	thumb,
1024	1013	thumbeb,
...	...	@@ -1028,8 +1017,6 @@ pub const Cpu = struct {
1028	1017	xtensa,
1029	1018	nvptx,
1030	1019	nvptx64,
1031		spir,
1032		spir64,
1033	1020	spirv,
1034	1021	spirv32,
1035	1022	spirv64,
...	...	@@ -1043,12 +1030,17 @@ pub const Cpu = struct {
1043	1030	// LLVM tags deliberately omitted:
1044	1031	// - aarch64_32
1045	1032	// - r600
	1033	// - sparcel
	1034	// - tce
	1035	// - tcele
1046	1036	// - le32
1047	1037	// - le64
1048	1038	// - amdil
1049	1039	// - amdil64
1050	1040	// - hsail
1051	1041	// - hsail64
	1042	// - spir
	1043	// - spir64
1052	1044	// - shave
1053	1045	// - renderscript32
1054	1046	// - renderscript64
...	...	@@ -1122,7 +1114,7 @@ pub const Cpu = struct {
1122	1114
1123	1115	pub inline fn isSPARC(arch: Arch) bool {
1124	1116	return switch (arch) {
1125		.sparc, .sparcel, .sparc64 => true,
	1117	.sparc, .sparc64 => true,
1126	1118	else => false,
1127	1119	};
1128	1120	}
...	...	@@ -1172,14 +1164,12 @@ pub const Cpu = struct {
1172	1164	.powerpc, .powerpcle => .PPC,
1173	1165	.riscv32 => .RISCV,
1174	1166	.sparc => .SPARC,
1175		.sparcel => .SPARC,
1176	1167	.thumb => .ARM,
1177	1168	.thumbeb => .ARM,
1178	1169	.x86 => .@"386",
1179	1170	.xcore => .XCORE,
1180	1171	.xtensa => .XTENSA,
1181	1172	.nvptx => .NONE,
1182		.spir => .NONE,
1183	1173	.kalimba => .CSR_KALIMBA,
1184	1174	.lanai => .LANAI,
1185	1175	.wasm32 => .NONE,
...	...	@@ -1192,7 +1182,6 @@ pub const Cpu = struct {
1192	1182	.riscv64 => .RISCV,
1193	1183	.x86_64 => .X86_64,
1194	1184	.nvptx64 => .NONE,
1195		.spir64 => .NONE,
1196	1185	.wasm64 => .NONE,
1197	1186	.amdgcn => .AMDGPU,
1198	1187	.bpfel => .BPF,
...	...	@@ -1225,14 +1214,12 @@ pub const Cpu = struct {
1225	1214	.powerpc, .powerpcle => .POWERPC,
1226	1215	.riscv32 => .RISCV32,
1227	1216	.sparc => .Unknown,
1228		.sparcel => .Unknown,
1229	1217	.thumb => .Thumb,
1230	1218	.thumbeb => .Thumb,
1231	1219	.x86 => .I386,
1232	1220	.xcore => .Unknown,
1233	1221	.xtensa => .Unknown,
1234	1222	.nvptx => .Unknown,
1235		.spir => .Unknown,
1236	1223	.kalimba => .Unknown,
1237	1224	.lanai => .Unknown,
1238	1225	.wasm32 => .Unknown,
...	...	@@ -1245,7 +1232,6 @@ pub const Cpu = struct {
1245	1232	.riscv64 => .RISCV64,
1246	1233	.x86_64 => .X64,
1247	1234	.nvptx64 => .Unknown,
1248		.spir64 => .Unknown,
1249	1235	.wasm64 => .Unknown,
1250	1236	.amdgcn => .Unknown,
1251	1237	.bpfel => .Unknown,
...	...	@@ -1279,7 +1265,6 @@ pub const Cpu = struct {
1279	1265	.msp430,
1280	1266	.nvptx,
1281	1267	.nvptx64,
1282		.sparcel,
1283	1268	.powerpcle,
1284	1269	.powerpc64le,
1285	1270	.riscv32,
...	...	@@ -1290,8 +1275,6 @@ pub const Cpu = struct {
1290	1275	.wasm64,
1291	1276	.xcore,
1292	1277	.thumb,
1293		.spir,
1294		.spir64,
1295	1278	.ve,
1296	1279	.spu_2,
1297	1280	// GPU bitness is opaque. For now, assume little endian.
...	...	@@ -1348,7 +1331,7 @@ pub const Cpu = struct {
1348	1331	.powerpc, .powerpcle, .powerpc64, .powerpc64le => "powerpc",
1349	1332	.amdgcn => "amdgpu",
1350	1333	.riscv32, .riscv64 => "riscv",
1351		.sparc, .sparc64, .sparcel => "sparc",
	1334	.sparc, .sparc64 => "sparc",
1352	1335	.s390x => "s390x",
1353	1336	.x86, .x86_64 => "x86",
1354	1337	.nvptx, .nvptx64 => "nvptx",
...	...	@@ -1375,7 +1358,7 @@ pub const Cpu = struct {
1375	1358	.powerpc, .powerpcle, .powerpc64, .powerpc64le => &powerpc.all_features,
1376	1359	.amdgcn => &amdgpu.all_features,
1377	1360	.riscv32, .riscv64 => &riscv.all_features,
1378		.sparc, .sparc64, .sparcel => &sparc.all_features,
	1361	.sparc, .sparc64 => &sparc.all_features,
1379	1362	.spirv32, .spirv64 => &spirv.all_features,
1380	1363	.s390x => &s390x.all_features,
1381	1364	.x86, .x86_64 => &x86.all_features,
...	...	@@ -1405,7 +1388,7 @@ pub const Cpu = struct {
1405	1388	.powerpc, .powerpcle, .powerpc64, .powerpc64le => comptime allCpusFromDecls(powerpc.cpu),
1406	1389	.amdgcn => comptime allCpusFromDecls(amdgpu.cpu),
1407	1390	.riscv32, .riscv64 => comptime allCpusFromDecls(riscv.cpu),
1408		.sparc, .sparc64, .sparcel => comptime allCpusFromDecls(sparc.cpu),
	1391	.sparc, .sparc64 => comptime allCpusFromDecls(sparc.cpu),
1409	1392	.spirv32, .spirv64 => comptime allCpusFromDecls(spirv.cpu),
1410	1393	.s390x => comptime allCpusFromDecls(s390x.cpu),
1411	1394	.x86, .x86_64 => comptime allCpusFromDecls(x86.cpu),
...	...	@@ -1497,7 +1480,7 @@ pub const Cpu = struct {
1497	1480	.riscv32 => &riscv.cpu.generic_rv32,
1498	1481	.riscv64 => &riscv.cpu.generic_rv64,
1499	1482	.spirv32, .spirv64 => &spirv.cpu.generic,
1500		.sparc, .sparcel => &sparc.cpu.generic,
	1483	.sparc => &sparc.cpu.generic,
1501	1484	.sparc64 => &sparc.cpu.v9, // 64-bit SPARC needs v9 as the baseline
1502	1485	.s390x => &s390x.cpu.generic,
1503	1486	.x86 => &x86.cpu.i386,
...	...	@@ -1519,7 +1502,7 @@ pub const Cpu = struct {
1519	1502	.x86 => &x86.cpu.pentium4,
1520	1503	.nvptx, .nvptx64 => &nvptx.cpu.sm_20,
1521	1504	.s390x => &s390x.cpu.arch8,
1522		.sparc, .sparcel => &sparc.cpu.v8,
	1505	.sparc => &sparc.cpu.v8,
1523	1506	.loongarch64 => &loongarch.cpu.loongarch64,
1524	1507
1525	1508	else => generic(arch),
...	...	@@ -1704,7 +1687,6 @@ pub const DynamicLinker = struct {
1704	1687	.linux => switch (cpu.arch) {
1705	1688	.x86,
1706	1689	.sparc,
1707		.sparcel,
1708	1690	=> init("/lib/ld-linux.so.2"),
1709	1691
1710	1692	.aarch64 => init("/lib/ld-linux-aarch64.so.1"),
...	...	@@ -1773,8 +1755,6 @@ pub const DynamicLinker = struct {
1773	1755	.msp430,
1774	1756	.amdgcn,
1775	1757	.xcore,
1776		.spir,
1777		.spir64,
1778	1758	.kalimba,
1779	1759	.lanai,
1780	1760	.ve,
...	...	@@ -1811,8 +1791,6 @@ pub const DynamicLinker = struct {
1811	1791
1812	1792	// TODO go over each item in this list and either move it to the above list, or
1813	1793	// implement the standard dynamic linker path code for it.
1814		.ananas,
1815		.cloudabi,
1816	1794	.fuchsia,
1817	1795	.ps3,
1818	1796	.zos,
...	...	@@ -1865,13 +1843,11 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
1865	1843	.powerpc,
1866	1844	.powerpcle,
1867	1845	.riscv32,
1868		.sparcel,
1869	1846	.thumb,
1870	1847	.thumbeb,
1871	1848	.x86,
1872	1849	.xcore,
1873	1850	.nvptx,
1874		.spir,
1875	1851	.kalimba,
1876	1852	.lanai,
1877	1853	.wasm32,
...	...	@@ -1890,7 +1866,6 @@ pub fn ptrBitWidth_cpu_abi(cpu: Cpu, abi: Abi) u16 {
1890	1866	.riscv64,
1891	1867	.x86_64,
1892	1868	.nvptx64,
1893		.spir64,
1894	1869	.wasm64,
1895	1870	.amdgcn,
1896	1871	.bpfel,
...	...	@@ -1927,7 +1902,6 @@ pub fn stackAlignment(target: Target) u16 {
1927	1902	.mips,
1928	1903	.mipsel,
1929	1904	.sparc,
1930		.sparcel,
1931	1905	=> 8,
1932	1906	.aarch64,
1933	1907	.aarch64_be,
...	...	@@ -2088,7 +2062,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
2088	2062	.s390x,
2089	2063	.sparc,
2090	2064	.sparc64,
2091		.sparcel,
2092	2065	.wasm32,
2093	2066	.wasm64,
2094	2067	.loongarch32,
...	...	@@ -2111,7 +2084,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
2111	2084	.solaris,
2112	2085	.illumos,
2113	2086	.haiku,
2114		.ananas,
2115	2087	.fuchsia,
2116	2088	.minix,
2117	2089	=> switch (target.cpu.arch) {
...	...	@@ -2195,7 +2167,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
2195	2167	.mips64el,
2196	2168	.sparc,
2197	2169	.sparc64,
2198		.sparcel,
2199	2170	.wasm32,
2200	2171	.wasm64,
2201	2172	.loongarch32,
...	...	@@ -2307,7 +2278,6 @@ pub fn c_type_bit_size(target: Target, c_type: CType) u16 {
2307	2278	.longdouble => return 80,
2308	2279	},
2309	2280
2310		.cloudabi,
2311	2281	.ps3,
2312	2282	.zos,
2313	2283	.rtems,
...	...	@@ -2375,7 +2345,6 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
2375	2345	.xcore,
2376	2346	.dxil,
2377	2347	.loongarch32,
2378		.spir,
2379	2348	.spirv32,
2380	2349	.kalimba,
2381	2350	.ve,
...	...	@@ -2392,13 +2361,11 @@ pub fn c_type_alignment(target: Target, c_type: CType) u16 {
2392	2361	.mips,
2393	2362	.mipsel,
2394	2363	.sparc,
2395		.sparcel,
2396	2364	.sparc64,
2397	2365	.lanai,
2398	2366	.nvptx,
2399	2367	.nvptx64,
2400	2368	.s390x,
2401		.spir64,
2402	2369	.spirv64,
2403	2370	=> 8,
2404	2371
...	...	@@ -2483,7 +2450,6 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
2483	2450	.xcore,
2484	2451	.dxil,
2485	2452	.loongarch32,
2486		.spir,
2487	2453	.spirv32,
2488	2454	.kalimba,
2489	2455	.ve,
...	...	@@ -2507,13 +2473,11 @@ pub fn c_type_preferred_alignment(target: Target, c_type: CType) u16 {
2507	2473	.mips,
2508	2474	.mipsel,
2509	2475	.sparc,
2510		.sparcel,
2511	2476	.sparc64,
2512	2477	.lanai,
2513	2478	.nvptx,
2514	2479	.nvptx64,
2515	2480	.s390x,
2516		.spir64,
2517	2481	.spirv64,
2518	2482	=> 8,
2519	2483

lib/std/atomic.zig-1

...	...	@@ -478,7 +478,6 @@ pub const cache_line = switch (builtin.cpu.arch) {
478	478	.riscv32,
479	479	.riscv64,
480	480	.sparc,
481		.sparcel,
482	481	.sparc64,
483	482	=> 32,
484	483

lib/std/builtin.zig+1-1

...	...	@@ -615,7 +615,7 @@ pub const VaList = switch (builtin.cpu.arch) {
615	615	else => VaListPowerPc,
616	616	},
617	617	.powerpc64, .powerpc64le => *u8,
618		.sparc, .sparcel, .sparc64 => *anyopaque,
	618	.sparc, .sparc64 => *anyopaque,
619	619	.spirv32, .spirv64 => *anyopaque,
620	620	.s390x => VaListS390x,
621	621	.wasm32, .wasm64 => *anyopaque,

lib/std/c.zig+3-3

...	...	@@ -5779,7 +5779,7 @@ pub const ucontext_t = switch (native_os) {
5779	5779	.x86 => 4,
5780	5780	.mips, .mipsel, .mips64, .mips64el => 14,
5781	5781	.arm, .armeb, .thumb, .thumbeb => 1,
5782		.sparc, .sparcel, .sparc64 => if (@sizeOf(usize) == 4) 43 else 8,
	5782	.sparc, .sparc64 => if (@sizeOf(usize) == 4) 43 else 8,
5783	5783	else => 0,
5784	5784	}
5785	5785	]u32,
...	...	@@ -6821,7 +6821,7 @@ pub const pthread_key_t = switch (native_os) {
6821	6821	pub const padded_pthread_spin_t = switch (native_os) {
6822	6822	.netbsd => switch (builtin.cpu.arch) {
6823	6823	.x86, .x86_64 => u32,
6824		.sparc, .sparcel, .sparc64 => u32,
	6824	.sparc, .sparc64 => u32,
6825	6825	else => pthread_spin_t,
6826	6826	},
6827	6827	else => void,
...	...	@@ -6834,7 +6834,7 @@ pub const pthread_spin_t = switch (native_os) {
6834	6834	.powerpc, .powerpc64, .powerpc64le => i32,
6835	6835	.x86, .x86_64 => u8,
6836	6836	.arm, .armeb, .thumb, .thumbeb => i32,
6837		.sparc, .sparcel, .sparc64 => u8,
	6837	.sparc, .sparc64 => u8,
6838	6838	.riscv32, .riscv64 => u32,
6839	6839	else => @compileError("undefined pthread_spin_t for this arch"),
6840	6840	},

lib/std/os/linux.zig+1-3

...	...	@@ -2496,7 +2496,7 @@ pub const E = switch (native_arch) {
2496	2496
2497	2497	pub const init = errnoFromSyscall;
2498	2498	},
2499		.sparc, .sparcel, .sparc64 => enum(u16) {
	2499	.sparc, .sparc64 => enum(u16) {
2500	2500	/// No error occurred.
2501	2501	SUCCESS = 0,
2502	2502
...	...	@@ -4843,7 +4843,6 @@ pub const MINSIGSTKSZ = switch (native_arch) {
4843	4843	=> 2048,
4844	4844	.loongarch64,
4845	4845	.sparc,
4846		.sparcel,
4847	4846	.sparc64,
4848	4847	=> 4096,
4849	4848	.aarch64,
...	...	@@ -4880,7 +4879,6 @@ pub const SIGSTKSZ = switch (native_arch) {
4880	4879	.aarch64_be,
4881	4880	.loongarch64,
4882	4881	.sparc,
4883		.sparcel,
4884	4882	.sparc64,
4885	4883	=> 16384,
4886	4884	.powerpc64,

lib/std/os/linux/ioctl.zig-1

...	...	@@ -11,7 +11,6 @@ const bits = switch (@import("builtin").cpu.arch) {
11	11	.powerpc64le,
12	12	.sparc,
13	13	.sparc64,
14		.sparcel,
15	14	=> .{ .size = 13, .dir = 3, .none = 1, .read = 2, .write = 4 },
16	15	else => .{ .size = 14, .dir = 2, .none = 0, .read = 2, .write = 1 },
17	16	};

src/Type.zig-3

...	...	@@ -1602,7 +1602,6 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
1602	1602	.amdgcn,
1603	1603	.riscv32,
1604	1604	.sparc,
1605		.sparcel,
1606	1605	.s390x,
1607	1606	.lanai,
1608	1607	.wasm32,
...	...	@@ -1647,11 +1646,9 @@ pub fn maxIntAlignment(target: std.Target, use_llvm: bool) u16 {
1647	1646	.csky,
1648	1647	.arc,
1649	1648	.m68k,
1650		.spir,
1651	1649	.kalimba,
1652	1650	.spirv,
1653	1651	.spirv32,
1654		.spir64,
1655	1652	.ve,
1656	1653	.spirv64,
1657	1654	.dxil,

src/Zcu.zig-3

...	...	@@ -3248,12 +3248,10 @@ pub fn atomicPtrAlignment(
3248	3248	.powerpcle,
3249	3249	.riscv32,
3250	3250	.sparc,
3251		.sparcel,
3252	3251	.thumb,
3253	3252	.thumbeb,
3254	3253	.x86,
3255	3254	.xcore,
3256		.spir,
3257	3255	.kalimba,
3258	3256	.lanai,
3259	3257	.wasm32,
...	...	@@ -3275,7 +3273,6 @@ pub fn atomicPtrAlignment(
3275	3273	.riscv64,
3276	3274	.sparc64,
3277	3275	.s390x,
3278		.spir64,
3279	3276	.wasm64,
3280	3277	.ve,
3281	3278	.spirv64,

src/codegen/llvm.zig+1-14

...	...	@@ -69,7 +69,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
69	69	.riscv64 => "riscv64",
70	70	.sparc => "sparc",
71	71	.sparc64 => "sparc64",
72		.sparcel => "sparcel",
73	72	.s390x => "s390x",
74	73	.thumb => "thumb",
75	74	.thumbeb => "thumbeb",
...	...	@@ -79,8 +78,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
79	78	.xtensa => "xtensa",
80	79	.nvptx => "nvptx",
81	80	.nvptx64 => "nvptx64",
82		.spir => "spir",
83		.spir64 => "spir64",
84	81	.spirv => "spirv",
85	82	.spirv32 => "spirv32",
86	83	.spirv64 => "spirv64",
...	...	@@ -136,8 +133,6 @@ pub fn targetTriple(allocator: Allocator, target: std.Target) ![]const u8 {
136	133	.opencl,
137	134	.glsl450,
138	135	.plan9,
139		.ananas,
140		.cloudabi,
141	136	.minix,
142	137	.contiki,
143	138	.other,
...	...	@@ -208,8 +203,6 @@ pub fn targetOs(os_tag: std.Target.Os.Tag) llvm.OSType {
208	203	.opencl,
209	204	.glsl450,
210	205	.plan9,
211		.ananas,
212		.cloudabi,
213	206	.minix,
214	207	.contiki,
215	208	=> .UnknownOS,
...	...	@@ -282,7 +275,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
282	275	.riscv64 => .riscv64,
283	276	.sparc => .sparc,
284	277	.sparc64 => .sparcv9, // In LLVM, sparc64 == sparcv9.
285		.sparcel => .sparcel,
286	278	.s390x => .systemz,
287	279	.thumb => .thumb,
288	280	.thumbeb => .thumbeb,
...	...	@@ -292,8 +284,6 @@ pub fn targetArch(arch_tag: std.Target.Cpu.Arch) llvm.ArchType {
292	284	.xtensa => .xtensa,
293	285	.nvptx => .nvptx,
294	286	.nvptx64 => .nvptx64,
295		.spir => .spir,
296		.spir64 => .spir64,
297	287	.spirv => .spirv,
298	288	.spirv32 => .spirv32,
299	289	.spirv64 => .spirv64,
...	...	@@ -473,7 +463,6 @@ const DataLayoutBuilder = struct {
473	463	.powerpcle,
474	464	.riscv32,
475	465	.sparc,
476		.sparcel,
477	466	.thumb,
478	467	.thumbeb,
479	468	.xtensa,
...	...	@@ -12008,7 +11997,7 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
12008	11997	llvm.LLVMInitializeRISCVAsmPrinter();
12009	11998	llvm.LLVMInitializeRISCVAsmParser();
12010	11999	},
12011		.sparc, .sparc64, .sparcel => {
	12000	.sparc, .sparc64 => {
12012	12001	llvm.LLVMInitializeSparcTarget();
12013	12002	llvm.LLVMInitializeSparcTargetInfo();
12014	12003	llvm.LLVMInitializeSparcTargetMC();
...	...	@@ -12095,8 +12084,6 @@ pub fn initializeLLVMTarget(arch: std.Target.Cpu.Arch) void {
12095	12084	},
12096	12085
12097	12086	// LLVM backends that have no initialization functions.
12098		.spir,
12099		.spir64,
12100	12087	.spirv,
12101	12088	.spirv32,
12102	12089	.spirv64,

src/glibc.zig+13-2

...	...	@@ -122,6 +122,17 @@ pub fn loadMetaData(gpa: Allocator, contents: []const u8) LoadMetaDataError!*ABI
122	122	return error.ZigInstallationCorrupt;
123	123	};
124	124	const arch_tag = std.meta.stringToEnum(std.Target.Cpu.Arch, arch_name) orelse {
	125	// TODO: Remove this on the next glibc abilists update.
	126	if (mem.eql(u8, arch_name, "sparcel")) {
	127	targets[i] = .{
	128	.arch = .sparc,
	129	.os = .linux,
	130	.abi = .gnu,
	131	};
	132
	133	continue;
	134	}
	135
125	136	log.err("abilists: unrecognized arch: '{s}'", .{arch_name});
126	137	return error.ZigInstallationCorrupt;
127	138	};
...	...	@@ -394,7 +405,7 @@ fn start_asm_path(comp: *Compilation, arena: Allocator, basename: []const u8) ![
394	405	const arch = comp.getTarget().cpu.arch;
395	406	const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le;
396	407	const is_aarch64 = arch == .aarch64 or arch == .aarch64_be;
397		const is_sparc = arch == .sparc or arch == .sparcel or arch == .sparc64;
	408	const is_sparc = arch == .sparc or arch == .sparc64;
398	409	const is_64 = comp.getTarget().ptrBitWidth() == 64;
399	410
400	411	const s = path.sep_str;
...	...	@@ -532,7 +543,7 @@ fn add_include_dirs_arch(
532	543	const is_x86 = arch == .x86 or arch == .x86_64;
533	544	const is_aarch64 = arch == .aarch64 or arch == .aarch64_be;
534	545	const is_ppc = arch == .powerpc or arch == .powerpc64 or arch == .powerpc64le;
535		const is_sparc = arch == .sparc or arch == .sparcel or arch == .sparc64;
	546	const is_sparc = arch == .sparc or arch == .sparc64;
536	547	const is_64 = target.ptrBitWidth() == 64;
537	548
538	549	const s = path.sep_str;

src/link/Elf.zig+1-1

...	...	@@ -4901,7 +4901,7 @@ fn getLDMOption(target: std.Target) ?[]const u8 {
4901	4901	.powerpc => return "elf32ppclinux",
4902	4902	.powerpc64 => return "elf64ppc",
4903	4903	.powerpc64le => return "elf64lppc",
4904		.sparc, .sparcel => return "elf32_sparc",
	4904	.sparc => return "elf32_sparc",
4905	4905	.sparc64 => return "elf64_sparc",
4906	4906	.mips => return "elf32btsmip",
4907	4907	.mipsel => return "elf32ltsmip",

src/link/Plan9/aout.zig+1-1

...	...	@@ -110,7 +110,7 @@ pub const R_MAGIC = _MAGIC(HDR_MAGIC, 28); // arm64
110	110	pub fn magicFromArch(arch: std.Target.Cpu.Arch) !u32 {
111	111	return switch (arch) {
112	112	.x86 => I_MAGIC,
113		.sparc => K_MAGIC, // TODO should sparc64 and sparcel go here?
	113	.sparc => K_MAGIC, // TODO should sparc64 go here?
114	114	.mips => V_MAGIC,
115	115	.arm => E_MAGIC,
116	116	.aarch64 => R_MAGIC,

src/target.zig+1-5

...	...	@@ -138,7 +138,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
138	138	.riscv64,
139	139	.sparc,
140	140	.sparc64,
141		.sparcel,
142	141	.s390x,
143	142	.thumb,
144	143	.thumbeb,
...	...	@@ -148,8 +147,6 @@ pub fn hasLlvmSupport(target: std.Target, ofmt: std.Target.ObjectFormat) bool {
148	147	.xtensa,
149	148	.nvptx,
150	149	.nvptx64,
151		.spir,
152		.spir64,
153	150	.spirv,
154	151	.spirv32,
155	152	.spirv64,
...	...	@@ -410,7 +407,7 @@ pub fn defaultFunctionAlignment(target: std.Target) Alignment {
410	407	return switch (target.cpu.arch) {
411	408	.arm, .armeb => .@"4",
412	409	.aarch64, .aarch64_be => .@"4",
413		.sparc, .sparcel, .sparc64 => .@"4",
	410	.sparc, .sparc64 => .@"4",
414	411	.riscv64 => .@"2",
415	412	else => .@"1",
416	413	};
...	...	@@ -425,7 +422,6 @@ pub fn minFunctionAlignment(target: std.Target) Alignment {
425	422	.riscv32,
426	423	.riscv64,
427	424	.sparc,
428		.sparcel,
429	425	.sparc64,
430	426	=> .@"2",
431	427	else => .@"1",

test/behavior/align.zig-1

...	...	@@ -95,7 +95,6 @@ test "alignment and size of structs with 128-bit fields" {
95	95	.amdgcn,
96	96	.riscv32,
97	97	.sparc,
98		.sparcel,
99	98	.s390x,
100	99	.lanai,
101	100	.wasm32,

test/llvm_targets.zig-2

...	...	@@ -87,8 +87,6 @@ const targets = [_]std.Target.Query{
87	87	.{ .cpu_arch = .sparc, .os_tag = .freestanding, .abi = .none },
88	88	.{ .cpu_arch = .sparc, .os_tag = .linux, .abi = .gnu },
89	89	.{ .cpu_arch = .sparc, .os_tag = .linux, .abi = .none },
90		.{ .cpu_arch = .sparcel, .os_tag = .freestanding, .abi = .none },
91		.{ .cpu_arch = .sparcel, .os_tag = .linux, .abi = .gnu },
92	90	.{ .cpu_arch = .sparc64, .os_tag = .freestanding, .abi = .none },
93	91	.{ .cpu_arch = .sparc64, .os_tag = .linux, .abi = .gnu },
94	92	//.{ .cpu_arch = .spirv32, .os_tag = .opencl, .abi = .none },

author	Andrew Kelley <andrew@ziglang.org> 2024-08-01 01:32:32-07:00
committer	GitHub <noreply@github.com> 2024-08-01 01:32:32-07:00
log	8f7cbaa4c0cebc22613a33d212569cf221d6a3df
tree	69f542e4fbe140e088924af02c731402f947c4d8
parent	f17f73b4fa5640b7f070b80ada5e52e28e93608d
parent	62a01851d9c433ea3f2e98cc986e75d32aece443
signature	Signed by PGP key B5690EEEBB952194

Merge pull request #20870 from alexrp/target-cleanup-3