| author |  Alex Rønne Petersen <alex@alexrp.com> 2026-04-15 22:48:17+02:00 |
| committer | Alex Rønne Petersen <alex@alexrp.com> 2026-04-16 16:00:21+02:00 |
| log | ab2f9ca50341ce6115f2839281a6e3c640271583 |
| tree | 76ab2c38f37d0e1641917cfb4b5fd85ba029c63e |
| parent | deb9b58cbc04516753c86a64a6c1b71b2a4196a2 |
| signature |  Signed by SSH key SHA256:7B/LJ7bpR1eX8aCXSr4mtd5M45VMPKcx9zY8e95b5QM |
std.os.linux: csky and xtensa also use aligned register pairs
1 files changed, 3 insertions(+), 1 deletions(-)
lib- std
lib/std/os/linux.zig+3-1
| ... | ... | @@ -566,9 +566,11 @@ fn getauxvalImpl(index: usize) callconv(.c) usize { |
| 566 | 566 | // in a even-aligned register pair. |
| 567 | 567 | const require_aligned_register_pair = |
| 568 | 568 | builtin.cpu.arch.isArm() or |
| 569 | builtin.cpu.arch == .csky or | |
| 569 | 570 | builtin.cpu.arch == .hexagon or |
| 570 | 571 | builtin.cpu.arch.isMIPS32() or |
| 571 | builtin.cpu.arch.isPowerPC32(); | |
| 572 | builtin.cpu.arch.isPowerPC32() or | |
| 573 | builtin.cpu.arch.isXtensa(); | |
| 572 | 574 | |
| 573 | 575 | // Split a 64bit value into a {LSB,MSB} pair. |
| 574 | 576 | // The LE/BE variants specify the endianness to assume. |