authorgravatar for 81774659+gracefuu@users.noreply.github.comgracefu <81774659+gracefuu@users.noreply.github.com> 2021-04-11 23:27:43+08:00
committergravatar for 81774659+gracefuu@users.noreply.github.comgracefu <81774659+gracefuu@users.noreply.github.com> 2021-04-16 15:21:17+08:00
logdc136627251c920713536807e0da922c140ca588
tree58b4bb3a70f40a573ad6995bdaf29e322d204725
parent1e63e8d8b6559855eca6efac6eec18f0546ecafd
signaturelock-open Commit is signed but in an unrecognized format.

stage2 x86_64: force 64 bit mode when loading address of GOT

Co-authored-by: joachimschmidt557 <joachim.schmidt557@outlook.com>

1 files changed, 4 insertions(+), 4 deletions(-)

src/codegen.zig+4-4
...@@ -2422,13 +2422,13 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -2422,13 +2422,13 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
2422 log.debug("got_addr = 0x{x}", .{got_addr});2422 log.debug("got_addr = 0x{x}", .{got_addr});
2423 switch (arch) {2423 switch (arch) {
2424 .x86_64 => {2424 .x86_64 => {
2425 try self.genSetReg(inst.base.src, Type.initTag(.u32), .rax, .{ .memory = got_addr });2425 try self.genSetReg(inst.base.src, Type.initTag(.u64), .rax, .{ .memory = got_addr });
2426 // callq *%rax2426 // callq *%rax
2427 try self.code.ensureCapacity(self.code.items.len + 2);2427 try self.code.ensureCapacity(self.code.items.len + 2);
2428 self.code.appendSliceAssumeCapacity(&[2]u8{ 0xff, 0xd0 });2428 self.code.appendSliceAssumeCapacity(&[2]u8{ 0xff, 0xd0 });
2429 },2429 },
2430 .aarch64 => {2430 .aarch64 => {
2431 try self.genSetReg(inst.base.src, Type.initTag(.u32), .x30, .{ .memory = got_addr });2431 try self.genSetReg(inst.base.src, Type.initTag(.u64), .x30, .{ .memory = got_addr });
2432 // blr x302432 // blr x30
2433 writeInt(u32, try self.code.addManyAsArray(4), Instruction.blr(.x30).toU32());2433 writeInt(u32, try self.code.addManyAsArray(4), Instruction.blr(.x30).toU32());
2434 },2434 },
...@@ -3862,7 +3862,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -3862,7 +3862,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
3862 if (self.bin_file.options.pie) {3862 if (self.bin_file.options.pie) {
3863 // RIP-relative displacement to the entry in the GOT table.3863 // RIP-relative displacement to the entry in the GOT table.
3864 const abi_size = ty.abiSize(self.target.*);3864 const abi_size = ty.abiSize(self.target.*);
3865 const encoder = try X8664Encoder.init(self.code, 7);3865 const encoder = try X8664Encoder.init(self.code, 10);
38663866
3867 // LEA reg, [<offset>]3867 // LEA reg, [<offset>]
38683868
...@@ -3870,7 +3870,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {...@@ -3870,7 +3870,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type {
3870 // After we encode the instruction, we will know that the displacement bytes3870 // After we encode the instruction, we will know that the displacement bytes
3871 // for [<offset>] will be at self.code.items.len - 4.3871 // for [<offset>] will be at self.code.items.len - 4.
3872 encoder.rex(.{3872 encoder.rex(.{
3873 .w = abi_size == 8,3873 .w = true, // force 64 bit because loading an address (to the GOT)
3874 .r = reg.isExtended(),3874 .r = reg.isExtended(),
3875 });3875 });
3876 encoder.opcode_1byte(0x8D);3876 encoder.opcode_1byte(0x8D);