| ... | ... | @@ -2422,13 +2422,13 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { |
| 2422 | 2422 | log.debug("got_addr = 0x{x}", .{got_addr}); |
| 2423 | 2423 | switch (arch) { |
| 2424 | 2424 | .x86_64 => { |
| 2425 | | try self.genSetReg(inst.base.src, Type.initTag(.u32), .rax, .{ .memory = got_addr }); |
| 2425 | try self.genSetReg(inst.base.src, Type.initTag(.u64), .rax, .{ .memory = got_addr }); |
| 2426 | 2426 | // callq *%rax |
| 2427 | 2427 | try self.code.ensureCapacity(self.code.items.len + 2); |
| 2428 | 2428 | self.code.appendSliceAssumeCapacity(&[2]u8{ 0xff, 0xd0 }); |
| 2429 | 2429 | }, |
| 2430 | 2430 | .aarch64 => { |
| 2431 | | try self.genSetReg(inst.base.src, Type.initTag(.u32), .x30, .{ .memory = got_addr }); |
| 2431 | try self.genSetReg(inst.base.src, Type.initTag(.u64), .x30, .{ .memory = got_addr }); |
| 2432 | 2432 | // blr x30 |
| 2433 | 2433 | writeInt(u32, try self.code.addManyAsArray(4), Instruction.blr(.x30).toU32()); |
| 2434 | 2434 | }, |
| ... | ... | @@ -3862,7 +3862,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { |
| 3862 | 3862 | if (self.bin_file.options.pie) { |
| 3863 | 3863 | // RIP-relative displacement to the entry in the GOT table. |
| 3864 | 3864 | const abi_size = ty.abiSize(self.target.*); |
| 3865 | | const encoder = try X8664Encoder.init(self.code, 7); |
| 3865 | const encoder = try X8664Encoder.init(self.code, 10); |
| 3866 | 3866 | |
| 3867 | 3867 | // LEA reg, [<offset>] |
| 3868 | 3868 | |
| ... | ... | @@ -3870,7 +3870,7 @@ fn Function(comptime arch: std.Target.Cpu.Arch) type { |
| 3870 | 3870 | // After we encode the instruction, we will know that the displacement bytes |
| 3871 | 3871 | // for [<offset>] will be at self.code.items.len - 4. |
| 3872 | 3872 | encoder.rex(.{ |
| 3873 | | .w = abi_size == 8, |
| 3873 | .w = true, // force 64 bit because loading an address (to the GOT) |
| 3874 | 3874 | .r = reg.isExtended(), |
| 3875 | 3875 | }); |
| 3876 | 3876 | encoder.opcode_1byte(0x8D); |